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https://github.com/openhwgroup/cva5.git
synced 2025-04-20 03:57:18 -04:00
Convert id_metadata from inferred LUTRAMs to LUTRAM modules
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
This commit is contained in:
Eric Matthews
parent
6c63d2724e
commit
e003b51f95
3 changed files with 119 additions and 105 deletions
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@ -81,18 +81,16 @@ module instruction_metadata_and_id_management
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output logic [$clog2(NUM_EXCEPTION_SOURCES)-1:0] current_exception_unit
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);
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//////////////////////////////////////////
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(* ramstyle = "MLAB, no_rw_check" *) logic [31:0] pc_table [MAX_IDS];
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(* ramstyle = "MLAB, no_rw_check" *) logic [31:0] instruction_table [MAX_IDS];
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(* ramstyle = "MLAB, no_rw_check" *) logic [0:0] valid_fetch_addr_table [MAX_IDS];
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logic [31:0] decode_pc;
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logic [31:0] decode_instruction;
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fetch_metadata_t decode_fetch_metadata;
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(* ramstyle = "MLAB, no_rw_check" *) logic [0:0] uses_rd_table [MAX_IDS];
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(* ramstyle = "MLAB, no_rw_check" *) logic [0:0] is_store_table [MAX_IDS];
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(* ramstyle = "MLAB, no_rw_check" *) phys_addr_t id_to_phys_rd_table [MAX_IDS];
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(* ramstyle = "MLAB, no_rw_check" *) logic [$bits(fetch_metadata_t)-1:0] fetch_metadata_table [MAX_IDS];
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(* ramstyle = "MLAB, no_rw_check" *) logic [$bits(exception_sources_t)-1:0] exception_unit_table [MAX_IDS];
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typedef struct packed {
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logic is_rd;
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logic is_store;
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} instruction_type_t;
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instruction_type_t decode_type;
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instruction_type_t retire_type [RETIRE_PORTS];
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id_t decode_id;
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id_t oldest_pre_issue_id;
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@ -115,60 +113,98 @@ module instruction_metadata_and_id_management
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////////////////////////////////////////////////////
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//Instruction Metadata
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//PC table
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//Number of read ports = 1 or 2 (decode stage + exception logic (if enabled))
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always_ff @ (posedge clk) begin
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if (pc_id_assigned)
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pc_table[pc_id] <= if_pc;
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end
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//PC table(s)
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lutram_1w_1r #(.DATA_TYPE(logic[31:0]), .DEPTH(MAX_IDS))
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pc_table (
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.clk(clk),
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.waddr(pc_id),
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.raddr(decode_id),
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.ram_write(pc_id_assigned),
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.new_ram_data(if_pc),
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.ram_data_out(decode_pc)
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);
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generate if (CONFIG.INCLUDE_M_MODE) begin : gen_pc_id_exception_support
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lutram_1w_1r #(.DATA_TYPE(logic[31:0]), .DEPTH(MAX_IDS))
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pc_table_exception (
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.clk(clk),
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.waddr(pc_id),
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.raddr(retire_ids_next[0]),
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.ram_write(pc_id_assigned),
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.new_ram_data(if_pc),
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.ram_data_out(oldest_pc)
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);
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end endgenerate
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////////////////////////////////////////////////////
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//Instruction table
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//Number of read ports = 1 (decode stage)
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always_ff @ (posedge clk) begin
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if (fetch_complete)
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instruction_table[fetch_id] <= fetch_instruction;
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end
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lutram_1w_1r #(.DATA_TYPE(logic[31:0]), .DEPTH(MAX_IDS))
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instruction_table (
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.clk(clk),
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.waddr(fetch_id),
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.raddr(decode_id),
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.ram_write(fetch_complete),
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.new_ram_data(fetch_instruction),
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.ram_data_out(decode_instruction)
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);
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////////////////////////////////////////////////////
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//Valid fetched address table
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//Number of read ports = 1 (decode stage)
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always_ff @ (posedge clk) begin
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if (fetch_complete)
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fetch_metadata_table[fetch_id] <= fetch_metadata;
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end
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lutram_1w_1r #(.DATA_TYPE(fetch_metadata_t), .DEPTH(MAX_IDS))
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fetch_metadata_table (
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.clk(clk),
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.waddr(fetch_id),
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.raddr(decode_id),
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.ram_write(fetch_complete),
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.new_ram_data(fetch_metadata),
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.ram_data_out(decode_fetch_metadata)
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);
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////////////////////////////////////////////////////
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//Uses rd table
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//Retire Instruction Type Table
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//Number of read ports = RETIRE_PORTS
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always_ff @ (posedge clk) begin
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if (decode_advance)
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uses_rd_table[decode_id] <= decode_uses_rd & |decode_rd_addr;
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end
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////////////////////////////////////////////////////
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//Is store table
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//Number of read ports = RETIRE_PORTS
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always_ff @ (posedge clk) begin
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if (decode_advance)
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is_store_table[decode_id] <= decode_is_store;
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end
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lutram_1w_mr #(.DATA_TYPE(instruction_type_t), .DEPTH(MAX_IDS), .NUM_READ_PORTS(RETIRE_PORTS))
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retire_instruction_type_table (
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.clk(clk),
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.waddr(decode_id),
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.raddr(retire_ids_next),
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.ram_write(decode_advance),
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.new_ram_data('{
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is_rd : (decode_uses_rd & |decode_rd_addr),
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is_store : decode_is_store
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}),
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.ram_data_out(retire_type)
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);
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////////////////////////////////////////////////////
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//id_to_phys_rd_table
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//Number of read ports = WB_GROUPS
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always_ff @ (posedge clk) begin
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if (decode_advance)
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id_to_phys_rd_table[decode_id] <= decode_phys_rd_addr;
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end
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id_t wb_ids [CONFIG.NUM_WB_GROUPS];
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always_comb for (int i = 0; i < CONFIG.NUM_WB_GROUPS; i++)
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wb_ids[i] = wb_packet[i].id;
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lutram_1w_mr #(.DATA_TYPE(phys_addr_t), .DEPTH(MAX_IDS), .NUM_READ_PORTS(CONFIG.NUM_WB_GROUPS))
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id_to_phys_rd_table (
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.clk(clk),
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.waddr(decode_id),
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.raddr(wb_ids),
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.ram_write(decode_advance),
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.new_ram_data(decode_phys_rd_addr),
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.ram_data_out(wb_phys_addr)
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);
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////////////////////////////////////////////////////
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//Exception unit table
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always_ff @ (posedge clk) begin
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if (decode_advance)
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exception_unit_table[decode_id] <= decode_exception_unit;
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end
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generate if (CONFIG.INCLUDE_M_MODE) begin : gen_id_exception_support
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lutram_1w_1r #(.DATA_TYPE(logic[$bits(exception_sources_t)-1:0]), .DEPTH(MAX_IDS))
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exception_unit_table (
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.clk(clk),
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.waddr(decode_id),
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.raddr(retire_ids_next[0]),
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.ram_write(decode_advance),
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.new_ram_data(decode_exception_unit),
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.ram_data_out(current_exception_unit)
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);
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end endgenerate
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////////////////////////////////////////////////////
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//ID Management
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@ -282,11 +318,6 @@ module instruction_metadata_and_id_management
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.in_use (id_waiting_for_writeback)
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);
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////////////////////////////////////////////////////
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//WB phys_addr lookup
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always_comb for (int i = 0; i < CONFIG.NUM_WB_GROUPS; i++)
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wb_phys_addr[i] = id_to_phys_rd_table[wb_packet[i].id];
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////////////////////////////////////////////////////
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//Retirer
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logic contiguous_retire;
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@ -294,15 +325,6 @@ module instruction_metadata_and_id_management
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logic id_ready_to_retire [RETIRE_PORTS];
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logic [LOG2_RETIRE_PORTS-1:0] retire_with_rd_sel;
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logic [LOG2_RETIRE_PORTS-1:0] retire_with_store_sel;
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logic [RETIRE_PORTS-1:0] retire_id_uses_rd;
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logic [RETIRE_PORTS-1:0] retire_id_is_store;
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logic [RETIRE_PORTS-1:0] retire_id_waiting_for_writeback;
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generate for (i = 0; i < RETIRE_PORTS; i++) begin : gen_retire_writeback
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assign retire_id_uses_rd[i] = uses_rd_table[retire_ids_next[i]];
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assign retire_id_is_store[i] = is_store_table[retire_ids_next[i]];
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assign retire_id_waiting_for_writeback[i] = id_waiting_for_writeback[i];
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end endgenerate
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//Supports retiring up to RETIRE_PORTS instructions. The retired block of instructions must be
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//contiguous and must start with the first retire port. Additionally, only one register file writing
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@ -315,29 +337,36 @@ module instruction_metadata_and_id_management
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contiguous_retire = ~gc.retire_hold;
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retire_with_rd_found = 0;
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retire_with_store_found = 0;
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retire_with_rd_sel = 0;
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retire_with_store_sel = 0;
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for (int i = 0; i < RETIRE_PORTS; i++) begin
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id_is_post_issue[i] = post_issue_count > ID_COUNTER_W'(i);
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id_ready_to_retire[i] = (id_is_post_issue[i] & contiguous_retire & ~id_waiting_for_writeback[i]);
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retire_port_valid_next[i] = id_ready_to_retire[i] & ~((retire_id_uses_rd[i] & retire_with_rd_found) | (retire_id_is_store[i] & retire_with_store_found));
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retire_port_valid_next[i] = id_ready_to_retire[i] & ~((retire_type[i].is_rd & retire_with_rd_found) | (retire_type[i].is_store & retire_with_store_found));
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retire_with_rd_found |= retire_port_valid_next[i] & retire_id_uses_rd[i];
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retire_with_store_found |= retire_port_valid_next[i] & retire_id_is_store[i];
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retire_with_rd_found |= retire_port_valid_next[i] & retire_type[i].is_rd;
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retire_with_store_found |= retire_port_valid_next[i] & retire_type[i].is_store;
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contiguous_retire &= retire_port_valid_next[i] & ~gc.exception_pending;
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if (retire_port_valid_next[i] & retire_type[i].is_rd)
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retire_with_rd_sel = LOG2_RETIRE_PORTS'(i);
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if (retire_port_valid_next[i] & retire_type[i].is_store)
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retire_with_store_sel = LOG2_RETIRE_PORTS'(i);
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end
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end
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//retire_next packet
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priority_encoder #(.WIDTH(RETIRE_PORTS))
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retire_with_rd_sel_encoder (
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.priority_vector (retire_id_uses_rd),
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.encoded_result (retire_with_rd_sel)
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);
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//retire_next packets
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assign wb_retire_next = '{
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id : retire_ids_next[retire_with_rd_sel],
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valid : retire_with_rd_found
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};
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assign store_retire_next = '{
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id : retire_ids_next[retire_with_store_sel],
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valid : retire_with_store_found
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};
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assign wb_retire_next.id = retire_ids_next[retire_with_rd_sel];
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assign wb_retire_next.valid = retire_with_rd_found;
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always_comb begin
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retire_count_next = 0;
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for (int i = 0; i < RETIRE_PORTS; i++) begin
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@ -346,42 +375,27 @@ module instruction_metadata_and_id_management
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end
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always_ff @ (posedge clk) begin
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wb_retire.valid <= wb_retire_next.valid;
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wb_retire.id <= wb_retire_next.id;
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wb_retire <= wb_retire_next;
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store_retire <= store_retire_next;
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retire_count <= gc.writeback_supress ? '0 : retire_count_next;
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for (int i = 0; i < RETIRE_PORTS; i++)
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retire_port_valid[i] <= retire_port_valid_next[i] & ~gc.writeback_supress;
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end
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priority_encoder #(.WIDTH(RETIRE_PORTS))
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retire_with_store_sel_encoder (
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.priority_vector (retire_id_is_store),
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.encoded_result (retire_with_store_sel)
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);
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assign store_retire_next.id = retire_ids_next[retire_with_store_sel];
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assign store_retire_next.valid = retire_with_store_found;
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always_ff @ (posedge clk) begin
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store_retire <= store_retire_next;
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end
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////////////////////////////////////////////////////
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//Outputs
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assign pc_id_available = ~inflight_count[LOG2_MAX_IDS];
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//Decode
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assign decode.id = decode_id;
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assign decode.valid = fetched_count_neg[LOG2_MAX_IDS];
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assign decode.pc = pc_table[decode_id];
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assign decode.instruction = instruction_table[decode_id];
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assign decode.fetch_metadata = CONFIG.INCLUDE_M_MODE ? fetch_metadata_table[decode_id] : '{ok : 1, error_code : INST_ACCESS_FAULT};
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//Exception Support
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generate if (CONFIG.INCLUDE_M_MODE) begin : gen_id_exception_support
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assign oldest_pc = pc_table[retire_ids_next[0]];
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assign current_exception_unit = exception_unit_table[retire_ids_next[0]];
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end endgenerate
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localparam fetch_metadata_t ADDR_OK = '{ok : 1, error_code : INST_ADDR_MISSALIGNED};
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assign decode = '{
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id : decode_id,
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valid : fetched_count_neg[LOG2_MAX_IDS],
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pc : decode_pc,
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instruction : decode_instruction,
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fetch_metadata : CONFIG.INCLUDE_M_MODE ? decode_fetch_metadata : ADDR_OK
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};
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////////////////////////////////////////////////////
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//End of Implementation
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@ -477,8 +477,8 @@ module cva5_sim
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assign NUM_RETIRE_PORTS = RETIRE_PORTS;
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generate for (genvar i = 0; i < RETIRE_PORTS; i++) begin
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assign retire_ports_pc[i] = cpu.id_block.pc_table[cpu.retire_ids[i]];
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assign retire_ports_instruction[i] = cpu.id_block.instruction_table[cpu.retire_ids[i]];
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assign retire_ports_pc[i] = cpu.id_block.pc_table.ram[cpu.retire_ids[i]];
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assign retire_ports_instruction[i] = cpu.id_block.instruction_table.ram[cpu.retire_ids[i]];
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assign retire_ports_valid[i] = cpu.retire_port_valid[i];
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end endgenerate
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@ -612,8 +612,8 @@ module cva5_sim
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assign NUM_RETIRE_PORTS = RETIRE_PORTS;
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generate for (genvar i = 0; i < RETIRE_PORTS; i++) begin
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assign retire_ports_pc[i] = cpu.id_block.pc_table[cpu.retire_ids[i]];
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assign retire_ports_instruction[i] = cpu.id_block.instruction_table[cpu.retire_ids[i]];
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assign retire_ports_pc[i] = cpu.id_block.pc_table.ram[cpu.retire_ids[i]];
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assign retire_ports_instruction[i] = cpu.id_block.instruction_table.ram[cpu.retire_ids[i]];
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assign retire_ports_valid[i] = cpu.retire_port_valid[i];
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end endgenerate
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