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Merge pull request #12 from e-matthews/nexys-script-improvements

Browse source 
Improvements for competition setup
This commit is contained in:
Mike Thompson 2023-04-04 21:02:07 -04:00 • committed by GitHub
commit e11f2e0864
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GPG key ID: 4AEE18F83AFDEB23
12 changed files with 83 additions and 72 deletions
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5
core/csr_unit.sv
View file

@ -76,8 +76,9 @@ module csr_unit
output logic [31:0] epc,
//Retire
input retire_packet_t retire,
input retire_packet_t wb_retire,
input id_t retire_ids [RETIRE_PORTS],
input logic [LOG2_RETIRE_PORTS : 0] retire_count,
//External
input interrupt_t s_interrupt,
@ -681,7 +682,7 @@ endgenerate
minst_ret_input_next[CONFIG.CSRS.NON_STANDARD_OPTIONS.COUNTER_W-1:32] = updated_csr[CONFIG.CSRS.NON_STANDARD_OPTIONS.COUNTER_W-33:0];
end
assign minst_ret_inc = {(LOG2_RETIRE_PORTS+1){~(CONFIG.CSRS.NON_STANDARD_OPTIONS.MINSTR_WRITEABLE & (mwrite_en(MINSTRET) | mwrite_en(MINSTRETH)))}} & retire.count;
assign minst_ret_inc = {(LOG2_RETIRE_PORTS+1){~(CONFIG.CSRS.NON_STANDARD_OPTIONS.MINSTR_WRITEABLE & (mwrite_en(MINSTRET) | mwrite_en(MINSTRETH)))}} & retire_count;
always_ff @(posedge clk) begin
if (rst)

15
core/cva5.sv
View file

@ -163,11 +163,12 @@ module cva5
logic [$clog2(CONFIG.NUM_WB_GROUPS)-1:0] decode_rs_wb_group [REGFILE_READ_PORTS];
//ID freeing
retire_packet_t retire;
retire_packet_t wb_retire;
retire_packet_t store_retire;
id_t retire_ids [RETIRE_PORTS];
id_t retire_ids_next [RETIRE_PORTS];
logic retire_port_valid [RETIRE_PORTS];
logic [LOG2_RETIRE_PORTS : 0] retire_count;
//Writeback
wb_packet_t wb_packet [CONFIG.NUM_WB_GROUPS];
phys_addr_t wb_phys_addr [CONFIG.NUM_WB_GROUPS];
@ -251,11 +252,12 @@ module cva5
.instruction_issued_with_rd (instruction_issued_with_rd),
.wb_packet (wb_packet),
.wb_phys_addr (wb_phys_addr),
.retire (retire),
.wb_retire (wb_retire),
.store_retire (store_retire),
.retire_ids (retire_ids),
.retire_ids_next (retire_ids_next),
.retire_port_valid(retire_port_valid),
.retire_count (retire_count),
.post_issue_count(post_issue_count),
.oldest_pc (oldest_pc),
.current_exception_unit (current_exception_unit)
@ -349,7 +351,7 @@ module cva5
.decode (decode_rename_interface),
.issue (issue), //packet
.instruction_issued_with_rd (instruction_issued_with_rd),
.retire (retire) //packet
.wb_retire (wb_retire)
);
////////////////////////////////////////////////////
@ -538,8 +540,9 @@ module cva5
.mret(mret),
.sret(sret),
.epc(epc),
.retire(retire),
.wb_retire (wb_retire),
.retire_ids(retire_ids),
.retire_count (retire_count),
.s_interrupt(s_interrupt),
.m_interrupt(m_interrupt)
);
@ -567,7 +570,7 @@ module cva5
.mret(mret),
.sret(sret),
.epc(epc),
.retire (retire),
.wb_retire (wb_retire),
.retire_ids (retire_ids),
.retire_ids_next (retire_ids_next),
.interrupt_taken(interrupt_taken),
@ -602,7 +605,7 @@ module cva5
.decode_stage (decode),
.issue_stage (issue),
.issue_stage_ready (issue_stage_ready),
.issue_phys_rs_addr (issue_phys_rs_addr),
.issue_rs_addr (issue_rs_addr),
.unit_needed (unit_needed[UNIT_IDS.DIV]),
.uses_rs (unit_uses_rs[UNIT_IDS.DIV]),
.uses_rd (unit_uses_rd[UNIT_IDS.DIV]),

3
core/cva5_types.sv
View file

@ -133,9 +133,8 @@ package cva5_types;
} wb_packet_t;
typedef struct packed{
id_t id;
logic valid;
id_t phys_id;
logic [LOG2_RETIRE_PORTS : 0] count;
} retire_packet_t;
typedef struct packed {

14
core/div_unit.sv
View file

@ -41,7 +41,7 @@ module div_unit
input issue_packet_t issue_stage,
input logic issue_stage_ready,
input phys_addr_t issue_phys_rs_addr [REGFILE_READ_PORTS],
input rs_addr_t issue_rs_addr [REGFILE_READ_PORTS],
input logic [31:0] rf [REGFILE_READ_PORTS],
unit_issue_interface.unit issue,
@ -112,7 +112,7 @@ module div_unit
////////////////////////////////////////////////////
//Result resuse (for div/rem pairs)
phys_addr_t prev_div_rs_addr [2];
rs_addr_t prev_div_rs_addr [2];
logic [1:0] div_rd_match;
logic prev_div_result_valid;
logic div_rs_overwrite;
@ -120,19 +120,19 @@ module div_unit
always_ff @(posedge clk) begin
if (issue.new_request)
prev_div_rs_addr <= issue_phys_rs_addr[RS1:RS2];
prev_div_rs_addr <= issue_rs_addr[RS1:RS2];
end
assign div_op_reuse = {prev_div_result_valid, prev_div_rs_addr[RS1], prev_div_rs_addr[RS2]} == {1'b1, issue_phys_rs_addr[RS1],issue_phys_rs_addr[RS2]};
assign div_op_reuse = {prev_div_result_valid, prev_div_rs_addr[RS1], prev_div_rs_addr[RS2]} == {1'b1, issue_rs_addr[RS1],issue_rs_addr[RS2]};
//Clear if prev div inputs are overwritten by another instruction
assign div_rd_match[RS1] = (issue_stage.phys_rd_addr == prev_div_rs_addr[RS1]);
assign div_rd_match[RS2] = (issue_stage.phys_rd_addr == prev_div_rs_addr[RS2]);
assign div_rd_match[RS1] = (issue_stage.rd_addr == prev_div_rs_addr[RS1]);
assign div_rd_match[RS2] = (issue_stage.rd_addr == prev_div_rs_addr[RS2]);
assign div_rs_overwrite = |div_rd_match;
set_clr_reg_with_rst #(.SET_OVER_CLR(1), .WIDTH(1), .RST_VALUE(0)) prev_div_result_valid_m (
.clk, .rst,
.set(issue.new_request),
.set(issue.new_request & ~((issue_stage.rd_addr == issue_rs_addr[RS1]) | (issue_stage.rd_addr == issue_rs_addr[RS2]))),
.clr((instruction_issued_with_rd & div_rs_overwrite) | gc.writeback_supress), //No instructions will be issued while gc.writeback_supress is asserted
.result(prev_div_result_valid)
);

2
core/gc_unit.sv
View file

@ -64,7 +64,7 @@ module gc_unit
input logic [31:0] epc,
//Retire
input retire_packet_t retire,
input retire_packet_t wb_retire,
input id_t retire_ids [RETIRE_PORTS],
input id_t retire_ids_next [RETIRE_PORTS],
input logic [$clog2(NUM_EXCEPTION_SOURCES)-1:0] current_exception_unit,

29
core/instruction_metadata_and_id_management.sv
View file

@ -67,11 +67,12 @@ module instruction_metadata_and_id_management
output phys_addr_t wb_phys_addr [CONFIG.NUM_WB_GROUPS],
//Retirer
output retire_packet_t retire,
output retire_packet_t wb_retire,
output retire_packet_t store_retire,
output id_t retire_ids [RETIRE_PORTS],
output id_t retire_ids_next [RETIRE_PORTS],
output logic retire_port_valid [RETIRE_PORTS],
output logic [LOG2_RETIRE_PORTS : 0] retire_count,
//CSR
output logic [LOG2_MAX_IDS:0] post_issue_count,
@ -103,11 +104,11 @@ module instruction_metadata_and_id_management
logic [LOG2_MAX_IDS:0] post_issue_count_next;
logic [LOG2_MAX_IDS:0] inflight_count;
retire_packet_t retire_next;
retire_packet_t wb_retire_next;
retire_packet_t store_retire_next;
logic retire_port_valid_next [RETIRE_PORTS];
logic [LOG2_RETIRE_PORTS : 0] retire_count_next;
genvar i;
////////////////////////////////////////////////////
//Implementation
@ -202,7 +203,7 @@ module instruction_metadata_and_id_management
if (rst)
retire_ids_next[i] <= LOG2_MAX_IDS'(i);
else
retire_ids_next[i] <= retire_ids_next[i] + LOG2_MAX_IDS'(retire_next.count);
retire_ids_next[i] <= retire_ids_next[i] + LOG2_MAX_IDS'(retire_count_next);
end
always_ff @ (posedge clk) begin
@ -230,7 +231,7 @@ module instruction_metadata_and_id_management
pre_issue_count <= pre_issue_count_next;
end
assign post_issue_count_next = post_issue_count + ID_COUNTER_W'(instruction_issued) - ID_COUNTER_W'(retire_next.count);
assign post_issue_count_next = post_issue_count + ID_COUNTER_W'(instruction_issued) - ID_COUNTER_W'(retire_count_next);
always_ff @ (posedge clk) begin
if (rst)
post_issue_count <= 0;
@ -334,20 +335,21 @@ module instruction_metadata_and_id_management
.encoded_result (retire_with_rd_sel)
);
assign retire_next.phys_id = retire_ids_next[retire_with_rd_sel];
assign retire_next.valid = retire_with_rd_found;
assign wb_retire_next.id = retire_ids_next[retire_with_rd_sel];
assign wb_retire_next.valid = retire_with_rd_found;
always_comb begin
retire_next.count = 0;
retire_count_next = 0;
for (int i = 0; i < RETIRE_PORTS; i++) begin
retire_next.count += retire_port_valid_next[i];
retire_count_next += retire_port_valid_next[i];
end
end
always_ff @ (posedge clk) begin
retire.valid <= retire_next.valid;
retire.phys_id <= retire_next.phys_id;
retire.count <= gc.writeback_supress ? '0 : retire_next.count;
wb_retire.valid <= wb_retire_next.valid;
wb_retire.id <= wb_retire_next.id;
retire_count <= gc.writeback_supress ? '0 : retire_count_next;
for (int i = 0; i < RETIRE_PORTS; i++)
retire_port_valid[i] <= retire_port_valid_next[i] & ~gc.writeback_supress;
end
@ -358,9 +360,8 @@ module instruction_metadata_and_id_management
.encoded_result (retire_with_store_sel)
);
assign store_retire_next.phys_id = retire_ids_next[retire_with_store_sel];
assign store_retire_next.id = retire_ids_next[retire_with_store_sel];
assign store_retire_next.valid = retire_with_store_found;
assign store_retire_next.count = 1;
always_ff @ (posedge clk) begin
store_retire <= store_retire_next;

10
core/renamer.sv
View file

@ -44,7 +44,7 @@ module renamer
input logic instruction_issued_with_rd,
//Retire response
input retire_packet_t retire
input retire_packet_t wb_retire
);
//////////////////////////////////////////
typedef struct packed{
@ -91,7 +91,7 @@ module renamer
);
//During post reset init, initialize FIFO with free list (registers 32-63)
assign free_list.potential_push = (gc.init_clear & ~clear_index[5]) | (retire.valid);
assign free_list.potential_push = (gc.init_clear & ~clear_index[5]) | (wb_retire.valid);
assign free_list.push = free_list.potential_push;
assign free_list.data_in = gc.init_clear ? {1'b1, clear_index[4:0]} : (gc.writeback_supress ? inuse_table_output.spec_phys_addr : inuse_table_output.previous_phys_addr);
@ -110,7 +110,7 @@ module renamer
inuse_table (
.clk (clk),
.waddr (issue.id),
.raddr (retire.phys_id),
.raddr (wb_retire.id),
.ram_write (instruction_issued_with_rd),
.new_ram_data (inuse_table_input),
.ram_data_out (inuse_table_output)
@ -135,12 +135,12 @@ module renamer
rs_addr_t spec_table_write_index;
rs_addr_t spec_table_write_index_mux [4];
assign spec_table_update = rename_valid | rollback | gc.init_clear | (retire.valid & gc.writeback_supress);
assign spec_table_update = rename_valid | rollback | gc.init_clear | (wb_retire.valid & gc.writeback_supress);
logic [1:0] spec_table_sel;
one_hot_to_integer #(.C_WIDTH(4)) spec_table_sel_one_hot_to_int (
.one_hot ({gc.init_clear, rollback, (retire.valid & gc.writeback_supress), 1'b0}),
.one_hot ({gc.init_clear, rollback, (wb_retire.valid & gc.writeback_supress), 1'b0}),
.int_out (spec_table_sel)
);

4
core/store_queue.sv
View file

@ -174,7 +174,7 @@ module store_queue
store_retire_table_lutram (
.clk(clk),
.waddr(sq.data_in.id),
.raddr(store_retire.phys_id),
.raddr(store_retire.id),
.ram_write(sq.push),
.new_ram_data(retire_table_in),
.ram_data_out(retire_table_out)
@ -187,7 +187,7 @@ module store_queue
non_forwarded_port (
.clk(clk),
.waddr(sq.data_in.id),
.raddr(store_retire.phys_id),
.raddr(store_retire.id),
.ram_write(sq.push),
.new_ram_data(sq.data_in.data),
.ram_data_out(wb_data[0])

14
examples/nexys/nexys_sim.sv
View file

@ -346,13 +346,13 @@ module cva5_sim
logic [3:0] stall_source_count;
///////////////
//Issue phys_rd to unit mem
//Issue rd_addr to unit mem
//Used for determining what outputs an operand stall is waiting on
logic [`ISSUE_P.NUM_UNITS-1:0] phys_addr_table [64];
logic [`ISSUE_P.NUM_UNITS-1:0] rd_addr_table [32];
always_ff @(posedge clk) begin
if (cpu.instruction_issued_with_rd)
phys_addr_table[`ISSUE_P.issue.phys_rd_addr] <= `ISSUE_P.unit_needed_issue_stage;
rd_addr_table[`ISSUE_P.issue.rd_addr] <= `ISSUE_P.unit_needed_issue_stage;
end
generate if (NEXYS_CONFIG.INCLUDE_ICACHE) begin
@ -410,9 +410,9 @@ module cva5_sim
//Issue Stall Source
for (int i = 0; i < REGFILE_READ_PORTS; i++) begin
stats[ISSUE_OPERAND_STALL_ON_LOAD_STAT] |= `ISSUE_P.issue.stage_valid & phys_addr_table[`ISSUE_P.issue_phys_rs_addr[i]][`ISSUE_P.UNIT_IDS.LS] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_MULTIPLY_STAT] |= EXAMPLE_CONFIG.INCLUDE_MUL & `ISSUE_P.issue.stage_valid & phys_addr_table[`ISSUE_P.issue_phys_rs_addr[i]][`ISSUE_P.UNIT_IDS.MUL] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_DIVIDE_STAT] |= EXAMPLE_CONFIG.INCLUDE_DIV & `ISSUE_P.issue.stage_valid & phys_addr_table[`ISSUE_P.issue_phys_rs_addr[i]][`ISSUE_P.UNIT_IDS.DIV] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_LOAD_STAT] |= `ISSUE_P.issue.stage_valid & rd_addr_table[`ISSUE_P.issue_rs_addr[i]][`ISSUE_P.UNIT_IDS.LS] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_MULTIPLY_STAT] |= EXAMPLE_CONFIG.INCLUDE_MUL & `ISSUE_P.issue.stage_valid & rd_addr_table[`ISSUE_P.issue_rs_addr[i]][`ISSUE_P.UNIT_IDS.MUL] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_DIVIDE_STAT] |= EXAMPLE_CONFIG.INCLUDE_DIV & `ISSUE_P.issue.stage_valid & rd_addr_table[`ISSUE_P.issue_rs_addr[i]][`ISSUE_P.UNIT_IDS.DIV] & `ISSUE_P.rs_conflict[i] ;
end
//LS Stats
@ -443,7 +443,7 @@ module cva5_sim
.end_collection (end_collection),
.stats (stats),
.instruction_mix_stats (instruction_mix_stats),
.retire (cpu.retire)
.retire_count (cpu.retire_count)
);
////////////////////////////////////////////////////

3
examples/nexys/scripts/system.tcl
View file

@ -45,6 +45,9 @@ set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project cva5-competition-baseline cva5-competition-baseline -part xc7a100tcsg324-1
set_property BOARD_PART digilentinc.com:nexys-a7-100t:part0:1.2 [current_project]
} else {
common::send_gid_msg -ssname BD::TCL -id 2100 -severity "ERROR" "Open project must be closed before running."
return -1
}

44
test_benches/sim_stats.sv
View file

@ -36,7 +36,7 @@ module sim_stats
input logic end_collection,
input logic stats [NUM_OF_STATS],
input logic [NUM_INSTRUCTION_MIX_STATS-1:0] instruction_mix_stats [RETIRE_PORTS],
input retire_packet_t retire
input logic [LOG2_RETIRE_PORTS:0] retire_count
);
int log_file;
logic en;
@ -47,36 +47,40 @@ module sim_stats
logic [63:0] instruction_mix_stat_count [NUM_INSTRUCTION_MIX_STATS-1:0];
logic [$clog2(RETIRE_PORTS):0] instruction_mix_inc [NUM_INSTRUCTION_MIX_STATS-1:0];
function real to_percent (input logic [63:0] a, input logic [63:0] b);
to_percent = 100.0 * real'(a)/real'(a + b);
endfunction
function void print_stats ();
$display("Fetch---------------------------------------------------------");
$display("Early Branch Correction : %-d", stat_count[FETCH_EARLY_BR_CORRECTION_STAT]);
$display("Sub Unit Stall : %-d", stat_count[FETCH_SUB_UNIT_STALL_STAT]);
$display("No ID available : %-d", stat_count[FETCH_ID_STALL_STAT]);
$display("Instruction Cache");
$display(" Hits : %-d", stat_count[FETCH_IC_HIT_STAT]);
$display(" Hits : %-d (%.2f%%)", stat_count[FETCH_IC_HIT_STAT], to_percent(stat_count[FETCH_IC_HIT_STAT], stat_count[FETCH_IC_MISS_STAT]));
$display(" Misses : %-d", stat_count[FETCH_IC_MISS_STAT]);
$display(" Arbiter stall : %-d", stat_count[FETCH_IC_ARB_STALL_STAT]);
$display("Branch Predictor");
$display(" Branches");
$display(" Correct : %-d", stat_count[FETCH_BP_BR_CORRECT_STAT]);
$display(" Correct : %-d (%.2f%%)", stat_count[FETCH_BP_BR_CORRECT_STAT], to_percent(stat_count[FETCH_BP_BR_CORRECT_STAT], stat_count[FETCH_BP_BR_MISPREDICT_STAT]));
$display(" Mispredict : %-d", stat_count[FETCH_BP_BR_MISPREDICT_STAT]);
$display(" Returns (RAS)");
$display(" Correct : %-d", stat_count[FETCH_BP_RAS_CORRECT_STAT]);
$display(" Correct : %-d (%.2f%%)", stat_count[FETCH_BP_RAS_CORRECT_STAT], to_percent(stat_count[FETCH_BP_RAS_CORRECT_STAT], stat_count[FETCH_BP_RAS_MISPREDICT_STAT]));
$display(" Mispredict : %-d", stat_count[FETCH_BP_RAS_MISPREDICT_STAT]);
$display("Issue---------------------------------------------------------");
$display("Stall Sources");
$display(" No Instruction : %-d", stat_count[ISSUE_NO_INSTRUCTION_STAT]);
$display(" No Instruction : %-d (%.2f%%)", stat_count[ISSUE_NO_INSTRUCTION_STAT], to_percent(stat_count[ISSUE_NO_INSTRUCTION_STAT], stat_count[ISSUE_UNIT_BUSY_STAT]+stat_count[ISSUE_OPERANDS_NOT_READY_STAT]+stat_count[ISSUE_HOLD_STAT]));
$display(" Max IDs Issued : %-d", stat_count[ISSUE_NO_ID_STAT]);
$display(" Flush : %-d", stat_count[ISSUE_FLUSH_STAT]);
$display(" Unit Busy : %-d", stat_count[ISSUE_UNIT_BUSY_STAT]);
$display(" Operands Not Ready : %-d", stat_count[ISSUE_OPERANDS_NOT_READY_STAT]);
$display(" Hold : %-d", stat_count[ISSUE_HOLD_STAT]);
$display(" Unit Busy : %-d (%.2f%%)", stat_count[ISSUE_UNIT_BUSY_STAT], to_percent(stat_count[ISSUE_UNIT_BUSY_STAT], stat_count[ISSUE_NO_INSTRUCTION_STAT]+stat_count[ISSUE_OPERANDS_NOT_READY_STAT]+stat_count[ISSUE_HOLD_STAT]));
$display(" Operands Not Ready : %-d (%.2f%%)", stat_count[ISSUE_OPERANDS_NOT_READY_STAT], to_percent(stat_count[ISSUE_OPERANDS_NOT_READY_STAT], stat_count[ISSUE_UNIT_BUSY_STAT]+stat_count[ISSUE_NO_INSTRUCTION_STAT]+stat_count[ISSUE_HOLD_STAT]));
$display(" Hold : %-d (%.2f%%)", stat_count[ISSUE_HOLD_STAT], to_percent(stat_count[ISSUE_HOLD_STAT], stat_count[ISSUE_UNIT_BUSY_STAT]+stat_count[ISSUE_NO_INSTRUCTION_STAT]+stat_count[ISSUE_OPERANDS_NOT_READY_STAT]));
$display(" Multi-Source : %-d", stat_count[ISSUE_MULTI_SOURCE_STAT]);
$display("Operand Stall Waiting On");
$display(" Load : %-d", stat_count[ISSUE_OPERAND_STALL_ON_LOAD_STAT]);
$display(" Multiply : %-d", stat_count[ISSUE_OPERAND_STALL_ON_MULTIPLY_STAT]);
$display(" Divide : %-d", stat_count[ISSUE_OPERAND_STALL_ON_DIVIDE_STAT]);
$display(" Load : %-d (%.2f%%)", stat_count[ISSUE_OPERAND_STALL_ON_LOAD_STAT], to_percent(stat_count[ISSUE_OPERAND_STALL_ON_LOAD_STAT], stat_count[ISSUE_OPERANDS_NOT_READY_STAT] - stat_count[ISSUE_OPERAND_STALL_ON_LOAD_STAT]));
$display(" Multiply : %-d (%.2f%%)", stat_count[ISSUE_OPERAND_STALL_ON_MULTIPLY_STAT], to_percent(stat_count[ISSUE_OPERAND_STALL_ON_MULTIPLY_STAT], stat_count[ISSUE_OPERANDS_NOT_READY_STAT] - stat_count[ISSUE_OPERAND_STALL_ON_MULTIPLY_STAT]));
$display(" Divide : %-d (%.2f%%)", stat_count[ISSUE_OPERAND_STALL_ON_DIVIDE_STAT], to_percent(stat_count[ISSUE_OPERAND_STALL_ON_DIVIDE_STAT], stat_count[ISSUE_OPERANDS_NOT_READY_STAT] - stat_count[ISSUE_OPERAND_STALL_ON_DIVIDE_STAT]));
$display("Operands Stall (Branch) : %-d", stat_count[ISSUE_OPERAND_STALL_FOR_BRANCH_STAT]);
$display("Store with Forwarded Data : %-d", stat_count[ISSUE_STORE_WITH_FORWARDED_DATA_STAT]);
$display("Divider Result Reuse : %-d", stat_count[ISSUE_DIVIDER_RESULT_REUSE_STAT]);
@ -85,7 +89,7 @@ module sim_stats
$display("Load Blocked by Store : %-d", stat_count[LSU_LOAD_BLOCKED_BY_STORE_STAT]);
$display("Sub Unit Stall : %-d", stat_count[LSU_SUB_UNIT_STALL_STAT]);
$display("Data Cache");
$display(" Hits : %-d", stat_count[LSU_DC_HIT_STAT]);
$display(" Hits : %-d (%.2f%%)", stat_count[LSU_DC_HIT_STAT], to_percent(stat_count[LSU_DC_HIT_STAT], stat_count[LSU_DC_MISS_STAT]));
$display(" Misses : %-d", stat_count[LSU_DC_MISS_STAT]);
$display(" Arbiter stall : %-d", stat_count[LSU_DC_ARB_STALL_STAT]);
@ -94,13 +98,13 @@ module sim_stats
$display("Runtime (cycles) : %-d", cycle_count);
$display("IPC : %-f", real'(instructions_retired)/real'(cycle_count));
$display("Instruction Mix");
$display(" Basic ALU : %-d", instruction_mix_stat_count[ALU_STAT]);
$display(" Branch or Jump : %-d", instruction_mix_stat_count[BR_STAT]);
$display(" Multiply : %-d", instruction_mix_stat_count[MUL_STAT]);
$display(" Divide : %-d", instruction_mix_stat_count[DIV_STAT]);
$display(" Load : %-d", instruction_mix_stat_count[LOAD_STAT]);
$display(" Store : %-d", instruction_mix_stat_count[STORE_STAT]);
$display(" Misc : %-d", instruction_mix_stat_count[MISC_STAT]);
$display(" Basic ALU : %-d (%.2f%%)", instruction_mix_stat_count[ALU_STAT], to_percent(instruction_mix_stat_count[ALU_STAT],instructions_retired - instruction_mix_stat_count[ALU_STAT]));
$display(" Branch or Jump : %-d (%.2f%%)", instruction_mix_stat_count[BR_STAT], to_percent(instruction_mix_stat_count[BR_STAT],instructions_retired - instruction_mix_stat_count[BR_STAT]));
$display(" Multiply : %-d (%.2f%%)", instruction_mix_stat_count[MUL_STAT], to_percent(instruction_mix_stat_count[MUL_STAT],instructions_retired - instruction_mix_stat_count[MUL_STAT]));
$display(" Divide : %-d (%.2f%%)", instruction_mix_stat_count[DIV_STAT], to_percent(instruction_mix_stat_count[DIV_STAT],instructions_retired - instruction_mix_stat_count[DIV_STAT]));
$display(" Load : %-d (%.2f%%)", instruction_mix_stat_count[LOAD_STAT], to_percent(instruction_mix_stat_count[LOAD_STAT],instructions_retired - instruction_mix_stat_count[LOAD_STAT]));
$display(" Store : %-d (%.2f%%)", instruction_mix_stat_count[STORE_STAT], to_percent(instruction_mix_stat_count[STORE_STAT],instructions_retired - instruction_mix_stat_count[STORE_STAT]));
$display(" Misc : %-d (%.2f%%)", instruction_mix_stat_count[MISC_STAT], to_percent(instruction_mix_stat_count[MISC_STAT],instructions_retired - instruction_mix_stat_count[MISC_STAT]));
$display("");
endfunction
@ -165,7 +169,7 @@ module sim_stats
instruction_mix_stat_count[i] <=0;
end
if (en) begin
instructions_retired <= instructions_retired + 64'(retire.count);
instructions_retired <= instructions_retired + 64'(retire_count);
cycle_count <= cycle_count + 1;
foreach (stat_count[i])
stat_count[i] <= stat_count[i] + 64'(stats[i]);

12
test_benches/verilator/cva5_sim.sv
View file

@ -483,11 +483,11 @@ module cva5_sim
//Issue phys_rd to unit mem
//Used for determining what outputs an operand stall is waiting on
logic [`ISSUE_P.NUM_UNITS-1:0] phys_addr_table [64];
logic [`ISSUE_P.NUM_UNITS-1:0] rd_addr_table [32];
always_ff @(posedge clk) begin
if (cpu.instruction_issued_with_rd)
phys_addr_table[`ISSUE_P.issue.phys_rd_addr] <= `ISSUE_P.unit_needed_issue_stage;
rd_addr_table[`ISSUE_P.issue.rd_addr] <= `ISSUE_P.unit_needed_issue_stage;
end
generate if (EXAMPLE_CONFIG.INCLUDE_ICACHE) begin
@ -545,9 +545,9 @@ module cva5_sim
//Issue Stall Source
for (int i = 0; i < REGFILE_READ_PORTS; i++) begin
stats[ISSUE_OPERAND_STALL_ON_LOAD_STAT] |= `ISSUE_P.issue.stage_valid & phys_addr_table[`ISSUE_P.issue_phys_rs_addr[i]][`ISSUE_P.UNIT_IDS.LS] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_MULTIPLY_STAT] |= EXAMPLE_CONFIG.INCLUDE_MUL & `ISSUE_P.issue.stage_valid & phys_addr_table[`ISSUE_P.issue_phys_rs_addr[i]][`ISSUE_P.UNIT_IDS.MUL] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_DIVIDE_STAT] |= EXAMPLE_CONFIG.INCLUDE_DIV & `ISSUE_P.issue.stage_valid & phys_addr_table[`ISSUE_P.issue_phys_rs_addr[i]][`ISSUE_P.UNIT_IDS.DIV] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_LOAD_STAT] |= `ISSUE_P.issue.stage_valid & rd_addr_table[`ISSUE_P.issue_rs_addr[i]][`ISSUE_P.UNIT_IDS.LS] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_MULTIPLY_STAT] |= EXAMPLE_CONFIG.INCLUDE_MUL & `ISSUE_P.issue.stage_valid & rd_addr_table[`ISSUE_P.issue_rs_addr[i]][`ISSUE_P.UNIT_IDS.MUL] & `ISSUE_P.rs_conflict[i] ;
stats[ISSUE_OPERAND_STALL_ON_DIVIDE_STAT] |= EXAMPLE_CONFIG.INCLUDE_DIV & `ISSUE_P.issue.stage_valid & rd_addr_table[`ISSUE_P.issue_rs_addr[i]][`ISSUE_P.UNIT_IDS.DIV] & `ISSUE_P.rs_conflict[i] ;
end
//LS Stats
@ -578,7 +578,7 @@ module cva5_sim
.end_collection (end_collection),
.stats (stats),
.instruction_mix_stats (instruction_mix_stats),
.retire (cpu.retire)
.retire_count (cpu.retire_count)
);
////////////////////////////////////////////////////