rst changes due to use of wb.ack

core/gc_unit.sv

@@ -364,7 +364,13 @@ module gc_unit(
 
     assign csr_ready_to_complete = processing_csr & (post_issue_count == 1);
     always_ff @(posedge clk) begin
-        csr_ready_to_complete_r <= csr_ready_to_complete;
+        if (rst)
+            csr_ready_to_complete_r <= 0;
+        else
+            csr_ready_to_complete_r <= csr_ready_to_complete;
+    end
+
+    always_ff @(posedge clk) begin
         csr_id <= instruction_id;
         if (issue.new_request) begin
             instruction_id <= issue.id;

core/mul_unit.sv

@@ -35,10 +35,10 @@ module mul_unit(
 
     logic signed [63:0] result;
     logic mulh [2];
-    logic done [2];
+    logic valid [2];
     id_t id [2];
 
-    logic rs1_signed, rs2_signed;
+    logic rs1_is_signed, rs2_is_signed;
     logic signed [32:0] rs1_ext, rs2_ext;
     logic signed [32:0] rs1_r, rs2_r;
 
@@ -46,15 +46,16 @@ module mul_unit(
     logic stage2_advance;
     ////////////////////////////////////////////////////
     //Implementation
-    assign rs1_signed = mul_inputs.op[1:0] inside {MULH_fn3[1:0], MULHSU_fn3[1:0]};//MUL doesn't matter
-    assign rs2_signed = mul_inputs.op[1:0] inside {MUL_fn3[1:0], MULH_fn3[1:0]};//MUL doesn't matter
+    assign rs1_is_signed = mul_inputs.op[1:0] inside {MULH_fn3[1:0], MULHSU_fn3[1:0]};//MUL doesn't matter
+    assign rs2_is_signed = mul_inputs.op[1:0] inside {MUL_fn3[1:0], MULH_fn3[1:0]};//MUL doesn't matter
 
-    assign rs1_ext = signed'({mul_inputs.rs1[31] & rs1_signed, mul_inputs.rs1});
-    assign rs2_ext = signed'({mul_inputs.rs2[31] & rs2_signed, mul_inputs.rs2});
+    assign rs1_ext = signed'({mul_inputs.rs1[31] & rs1_is_signed, mul_inputs.rs1});
+    assign rs2_ext = signed'({mul_inputs.rs2[31] & rs2_is_signed, mul_inputs.rs2});
 
+    //Pipeline advancement control signals
     assign issue.ready = stage1_advance;
-    assign stage1_advance = ~done[0] | stage2_advance;
-    assign stage2_advance = ~done[1] | wb.ack;
+    assign stage1_advance = ~valid[0] | stage2_advance;
+    assign stage2_advance = ~valid[1] | wb.ack;
 
     //Input and output registered Multiply
     always_ff @ (posedge clk) begin
@@ -67,24 +68,34 @@ module mul_unit(
         end
     end
 
+    //Attribute Pipeline
     always_ff @ (posedge clk) begin
         if (stage1_advance) begin
             mulh[0] <= (mul_inputs.op[1:0] != MUL_fn3[1:0]);
             id[0] <= issue.id;
-            done[0] <= issue.new_request;
         end
         if (stage2_advance) begin
             mulh[1] <= mulh[0];
             id[1] <= id[0];
-            done[1] <= done[0];
         end
     end
 
-    //Issue/write-back handshaking
+    //Valid/Done Pipeline
+    always_ff @ (posedge clk) begin
+        if (rst)
+            valid <= '{default: 0};
+        else begin
+            valid[0] <= stage1_advance ? issue.new_request : valid[0];
+            valid[1] <= stage2_advance ? valid[0] : valid[1];
+        end
+    end
+
+    //WB interface
     ////////////////////////////////////////////////////
     assign wb.rd = mulh[1] ? result[63:32] : result[31:0];
-    assign wb.done = done[1];
+    assign wb.done = valid[1];
     assign wb.id = id[1];
+
     ////////////////////////////////////////////////////
     //End of Implementation
     ////////////////////////////////////////////////////