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l1 arbiter clean up
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Eric Matthews
parent
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commit
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2 changed files with 55 additions and 123 deletions
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@ -139,17 +139,8 @@ interface l1_arbiter_request_interface;
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logic request;
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logic ack;
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function l2_request_t to_l2 (input bit[L2_SUB_ID_W-1:0] sub_id);
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to_l2.addr = addr[31:2];
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to_l2.rnw = rnw;
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to_l2.be = be;
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to_l2.is_amo = is_amo;
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to_l2.amo_type_or_burst_size = is_amo ? amo : size;
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to_l2.sub_id = sub_id;
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endfunction
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modport master (output addr, data, rnw, be, size, is_amo, amo, request, input ack);
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modport slave (import to_l2, input addr, data, rnw, be, size, is_amo, amo, request, output ack);
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modport slave (input addr, data, rnw, be, size, is_amo, amo, request, output ack);
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modport formal (input addr, data, rnw, be, size, is_amo, amo, request, ack);
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endinterface
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@ -40,142 +40,83 @@ module l1_arbiter
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l1_arbiter_return_interface.slave l1_response[L1_CONNECTIONS-1:0]
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);
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l2_request_t[L1_CONNECTIONS-1:0] l2_requests;
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l2_request_t [L1_CONNECTIONS-1:0] l2_requests;
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logic [L1_CONNECTIONS-1:0] requests;
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logic [L1_CONNECTIONS-1:0] acks;
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logic [((L1_CONNECTIONS == 1) ? 0 : ($clog2(L1_CONNECTIONS)-1)) : 0] arb_sel;
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logic push_ready;
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logic request_exists;
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////////////////////////////////////////////////////
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//Implementation
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//Interface to array
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generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin
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assign requests[i] = l1_request[i].request;
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assign l1_request[i].ack = acks[i];
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end endgenerate
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//////////////////////////////////////
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genvar i;
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generate
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for (i=0; i <L1_CONNECTIONS; i++) begin
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assign requests[i] = l1_request[i].request;
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assign l1_request[i].ack = acks[i];
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end
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endgenerate
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generate
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if (USE_DCACHE && USE_DTAG_INVALIDATIONS)
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assign l2.inv_ack = l1_response[L1_DCACHE_ID].inv_ack;
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else
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assign l2.inv_ack = l2.inv_valid;
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endgenerate
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//Always accept L2 data
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assign l2.rd_data_ack = l2.rd_data_valid;
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//Always accept store-conditional result
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assign sc_complete = l2.con_valid;
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assign sc_success = l2.con_result;
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//arbiter can pop address FIFO at a different rate than the data FIFO, so check that both have space.
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assign push_ready = ~l2.request_full & ~l2.data_full;
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//Arbiter can pop address FIFO at a different rate than the data FIFO, so check that both have space.
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assign push_ready = ~(l2.request_full | l2.data_full);
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assign request_exists = |requests;
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assign l2.request_push = push_ready & request_exists;
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//priority 0-to-n
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logic busy;
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always_comb begin
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acks[0] = l1_request[0].request & push_ready;//L1_DCACHE_ID
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busy = l1_request[0].request;
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for (int i = 1; i < L1_CONNECTIONS; i++) begin
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acks[i] = requests[i] & push_ready & ~busy;
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busy |= requests[i];
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end
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end
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////////////////////////////////////////////////////
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//Dcache Specific
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assign l2.wr_data_push = USE_DCACHE & (push_ready & l1_request[L1_DCACHE_ID].request & ~l1_request[L1_DCACHE_ID].rnw); //Assumes data cache has highest priority
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assign l2.wr_data = l1_request[L1_DCACHE_ID].data;
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assign l2.inv_ack = USE_DTAG_INVALIDATIONS ? l1_response[L1_DCACHE_ID].inv_ack : l2.inv_valid;
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assign l1_response[L1_DCACHE_ID].inv_addr = l2.inv_addr;
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assign l1_response[L1_DCACHE_ID].inv_valid = USE_DTAG_INVALIDATIONS & l2.inv_valid;
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generate
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if (USE_DCACHE) begin
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assign l2.wr_data_push = push_ready & l1_request[L1_DCACHE_ID].request & ~l1_request[L1_DCACHE_ID].rnw; //Assumes data cache has highest priority
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assign l2.wr_data = l1_request[L1_DCACHE_ID].data;
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////////////////////////////////////////////////////
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//Interface mapping
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generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin
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always_comb begin
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l2_requests[i].addr = l1_request[i].addr[31:2];
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l2_requests[i].rnw = l1_request[i].rnw;
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l2_requests[i].be = l1_request[i].be;
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l2_requests[i].is_amo = l1_request[i].is_amo;
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l2_requests[i].amo_type_or_burst_size = l1_request[i].size;
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l2_requests[i].sub_id = L2_SUB_ID_W'(i);
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end
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else begin
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assign l2.wr_data_push = 0;
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assign l2.wr_data = 0;
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end
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if (USE_DTAG_INVALIDATIONS) begin
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assign l1_response[L1_DCACHE_ID].inv_addr = l2.inv_addr;
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assign l1_response[L1_DCACHE_ID].inv_valid = l2.inv_valid;
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end
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else begin
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assign l1_response[L1_DCACHE_ID].inv_addr = 0;
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assign l1_response[L1_DCACHE_ID].inv_valid = 0;
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end
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endgenerate
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generate if (USE_DCACHE) begin
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always_comb begin
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l2_requests[L1_DCACHE_ID].addr = l1_request[L1_DCACHE_ID].addr[31:2];
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l2_requests[L1_DCACHE_ID].rnw = l1_request[L1_DCACHE_ID].rnw;
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l2_requests[L1_DCACHE_ID].be = l1_request[L1_DCACHE_ID].be;
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l2_requests[L1_DCACHE_ID].is_amo = l1_request[L1_DCACHE_ID].is_amo;
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l2_requests[L1_DCACHE_ID].amo_type_or_burst_size = l1_request[L1_DCACHE_ID].is_amo ? l1_request[L1_DCACHE_ID].amo : l1_request[L1_DCACHE_ID].size;
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l2_requests[L1_DCACHE_ID].sub_id = L1_DCACHE_ID;
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end
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end
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endgenerate
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generate if (USE_ICACHE) begin
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always_comb begin
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l2_requests[L1_ICACHE_ID].addr = l1_request[L1_ICACHE_ID].addr[31:2];
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l2_requests[L1_ICACHE_ID].rnw = l1_request[L1_ICACHE_ID].rnw;
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l2_requests[L1_ICACHE_ID].be = l1_request[L1_ICACHE_ID].be;
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l2_requests[L1_ICACHE_ID].is_amo = l1_request[L1_ICACHE_ID].is_amo;
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l2_requests[L1_ICACHE_ID].amo_type_or_burst_size = l1_request[L1_ICACHE_ID].size;
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l2_requests[L1_ICACHE_ID].sub_id = L1_ICACHE_ID;
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end
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end
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endgenerate
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generate if (ENABLE_S_MODE) begin
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always_comb begin
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l2_requests[L1_DMMU_ID].addr = l1_request[L1_DMMU_ID].addr[31:2];
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l2_requests[L1_DMMU_ID].rnw = l1_request[L1_DMMU_ID].rnw;
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l2_requests[L1_DMMU_ID].be = l1_request[L1_DMMU_ID].be;
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l2_requests[L1_DMMU_ID].is_amo = l1_request[L1_DMMU_ID].is_amo;
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l2_requests[L1_DMMU_ID].amo_type_or_burst_size = l1_request[L1_DMMU_ID].size;
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l2_requests[L1_DMMU_ID].sub_id = L1_DMMU_ID;
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l2_requests[L1_IMMU_ID].addr = l1_request[L1_IMMU_ID].addr[31:2];
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l2_requests[L1_IMMU_ID].rnw = l1_request[L1_IMMU_ID].rnw;
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l2_requests[L1_IMMU_ID].be = l1_request[L1_IMMU_ID].be;
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l2_requests[L1_IMMU_ID].is_amo = l1_request[L1_IMMU_ID].is_amo;
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l2_requests[L1_IMMU_ID].amo_type_or_burst_size = l1_request[L1_IMMU_ID].size;
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l2_requests[L1_IMMU_ID].sub_id = L1_IMMU_ID;
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end
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end
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endgenerate
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end endgenerate
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////////////////////////////////////////////////////
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//Arbitration
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priority_encoder
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#(.WIDTH(L1_CONNECTIONS))
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arb_encoder
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(
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.priority_vector (requests),
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.encoded_result (arb_sel)
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);
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always_comb begin
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l2.addr = l2_requests[L1_CONNECTIONS-1].addr;
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l2.rnw = l2_requests[L1_CONNECTIONS-1].rnw;
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l2.be = l2_requests[L1_CONNECTIONS-1].be;
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l2.is_amo = l2_requests[L1_CONNECTIONS-1].is_amo;
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l2.amo_type_or_burst_size = l2_requests[L1_CONNECTIONS-1].amo_type_or_burst_size;
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l2.sub_id = l2_requests[L1_CONNECTIONS-1].sub_id;
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for (int i = L1_CONNECTIONS-2; i >= 0; i--) begin
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if (requests[i]) begin
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l2.addr = l2_requests[i].addr;
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l2.rnw = l2_requests[i].rnw;
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l2.be = l2_requests[i].be;
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l2.is_amo = l2_requests[i].is_amo;
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l2.amo_type_or_burst_size = l2_requests[i].amo_type_or_burst_size;
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l2.sub_id = l2_requests[i].sub_id;
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end
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end
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acks = '0;
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acks[arb_sel] = l2.request_push;
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end
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generate
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for (i=0; i <L1_CONNECTIONS; i++) begin
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assign l1_response[i].data = l2.rd_data;
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assign l1_response[i].data_valid = l2.rd_data_valid && (l2.rd_sub_id == i);
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end
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endgenerate
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assign l2.addr = l2_requests[arb_sel].addr;
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assign l2.rnw = l2_requests[arb_sel].rnw;
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assign l2.be = l2_requests[arb_sel].be;
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assign l2.is_amo = l2_requests[arb_sel].is_amo;
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assign l2.amo_type_or_burst_size = l2_requests[arb_sel].amo_type_or_burst_size;
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assign l2.sub_id = l2_requests[arb_sel].sub_id;
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generate for (genvar i = 0; i < L1_CONNECTIONS; i++) begin
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assign l1_response[i].data = l2.rd_data;
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assign l1_response[i].data_valid = l2.rd_data_valid && (l2.rd_sub_id == i);
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end endgenerate
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endmodule
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