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Merge pull request #7 from flmeisel/axi_wstrb_fix
L2: Move be (i.e. wstrb for AXI) into the data FIFO (Fixes #6)
This commit is contained in:
Mike Thompson
GitHub
commit
ea96a5ccb2
8 changed files with 75 additions and 57 deletions
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@ -182,7 +182,7 @@ module axi_to_arb
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assign axi_wdata = read_modify_write ? amo_result_r : l2.wr_data;
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assign axi_wstrb =read_modify_write ? '1 : l2.be;
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assign axi_wstrb = read_modify_write ? '1 : l2.wr_data_be;
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//Done when read request sent, or slave ack on write data
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@ -78,6 +78,7 @@ module l1_arbiter
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//Dcache Specific
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assign l2.wr_data_push = CONFIG.INCLUDE_DCACHE & (push_ready & l1_request[L1_DCACHE_ID].request & ~l1_request[L1_DCACHE_ID].rnw); //Assumes data cache has highest priority
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assign l2.wr_data = l1_request[L1_DCACHE_ID].data;
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assign l2.wr_data_be = l1_request[L1_DCACHE_ID].be;
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assign l2.inv_ack = CONFIG.DCACHE.USE_EXTERNAL_INVALIDATIONS ? l1_response[L1_DCACHE_ID].inv_ack : l2.inv_valid;
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assign l1_response[L1_DCACHE_ID].inv_addr = l2.inv_addr;
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@ -89,7 +90,6 @@ module l1_arbiter
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always_comb begin
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l2_requests[i].addr = l1_request[i].addr[31:2];
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l2_requests[i].rnw = l1_request[i].rnw;
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l2_requests[i].be = l1_request[i].be;
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l2_requests[i].is_amo = l1_request[i].is_amo;
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l2_requests[i].amo_type_or_burst_size = l1_request[i].size;
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l2_requests[i].sub_id = L2_SUB_ID_W'(i);
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@ -113,7 +113,6 @@ module l1_arbiter
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assign l2.addr = l2_requests[arb_sel].addr;
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assign l2.rnw = l2_requests[arb_sel].rnw;
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assign l2.be = l2_requests[arb_sel].be;
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assign l2.is_amo = l2_requests[arb_sel].is_amo;
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assign l2.amo_type_or_burst_size = l2_requests[arb_sel].amo_type_or_burst_size;
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assign l2.sub_id = l2_requests[arb_sel].sub_id;
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@ -38,11 +38,14 @@ module l1_to_wishbone
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localparam MAX_REQUESTS = 32;
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fifo_interface #(.DATA_WIDTH($bits(l2_request_t))) request_fifo ();
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fifo_interface #(.DATA_WIDTH(32)) data_fifo ();
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fifo_interface #(.DATA_WIDTH($bits(l2_data_request_t))) data_fifo ();
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l2_request_t request_in;
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l2_request_t request;
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l2_data_request_t data_request_in;
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l2_data_request_t data_request;
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logic request_complete;
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////////////////////////////////////////////////////
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//Implementation
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@ -51,11 +54,10 @@ module l1_to_wishbone
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//Repack input attributes
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assign request_in.addr = cpu.addr;
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assign request_in.be = cpu.be;
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assign request_in.rnw = cpu.rnw;
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assign request_in.is_amo = cpu.is_amo;
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assign request_in.amo_type_or_burst_size = cpu.amo_type_or_burst_size;
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assign request_in.sub_id = cpu.sub_id;
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assign request_in.rnw = cpu.rnw;
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assign request_in.is_amo = cpu.is_amo;
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assign request_in.amo_type_or_burst_size = cpu.amo_type_or_burst_size;
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assign request_in.sub_id = cpu.sub_id;
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assign request_fifo.push = cpu.request_push;
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assign request_fifo.potential_push = cpu.request_push;
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@ -63,10 +65,14 @@ module l1_to_wishbone
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assign request_fifo.data_in = request_in;
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assign request = request_fifo.data_out;
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assign data_request_in.data = cpu.wr_data;
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assign data_request_in.be = cpu.wr_data_be;
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assign data_fifo.push = cpu.wr_data_push;
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assign data_fifo.potential_push = cpu.wr_data_push;
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assign data_fifo.pop = wishbone.we & wishbone.ack;
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assign data_fifo.data_in = cpu.wr_data;
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assign data_fifo.data_in = data_request_in;
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assign data_request = data_fifo.data_out;
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cva5_fifo #(.DATA_WIDTH($bits(l2_request_t)), .FIFO_DEPTH(MAX_REQUESTS))
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request_fifo_block (
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@ -74,7 +80,7 @@ module l1_to_wishbone
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.rst (rst),
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.fifo (request_fifo)
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);
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cva5_fifo #(.DATA_WIDTH(32), .FIFO_DEPTH(MAX_REQUESTS))
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cva5_fifo #(.DATA_WIDTH($bits(l2_data_request_t)), .FIFO_DEPTH(MAX_REQUESTS))
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data_fifo_block (
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.clk (clk),
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.rst (rst),
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@ -100,10 +106,10 @@ module l1_to_wishbone
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assign wishbone.adr[29:5] = request.addr[29:5];
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assign wishbone.adr[4:0] = (request.addr[4:0] & ~burst_size) | (burst_count & burst_size);
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assign wishbone.sel = request.rnw ? '1 : request.be;
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assign wishbone.sel = request.rnw ? '1 : data_request.be;
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assign wishbone.we = ~request.rnw;
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assign wishbone.dat_w = data_fifo.data_out;
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assign wishbone.dat_w = data_request.data;
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assign wishbone.stb = request_fifo.valid;
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assign wishbone.cyc = request_fifo.valid;
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@ -38,19 +38,20 @@ module l2_arbiter
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//FIFO interfaces
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fifo_interface #(.DATA_WIDTH($bits(l2_request_t))) input_fifos [L2_NUM_PORTS-1:0]();
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fifo_interface #(.DATA_WIDTH(32)) input_data_fifos [L2_NUM_PORTS-1:0]();
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fifo_interface #(.DATA_WIDTH($bits(l2_data_request_t))) input_data_fifos [L2_NUM_PORTS-1:0]();
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fifo_interface #(.DATA_WIDTH(30)) inv_response_fifos [L2_NUM_PORTS-1:0]();
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fifo_interface #(.DATA_WIDTH(32 + L2_SUB_ID_W)) returndata_fifos [L2_NUM_PORTS-1:0]();
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fifo_interface #(.DATA_WIDTH($bits(l2_mem_request_t))) mem_addr_fifo();
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fifo_interface #(.DATA_WIDTH(32)) mem_data_fifo();
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fifo_interface #(.DATA_WIDTH($bits(l2_data_request_t))) mem_data_fifo();
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fifo_interface #(.DATA_WIDTH($bits(l2_data_attributes_t))) data_attributes();
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fifo_interface #(.DATA_WIDTH(32 + L2_ID_W)) mem_returndata_fifo();
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l2_mem_request_t mem_addr_fifo_data_out;
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l2_request_t requests_in[L2_NUM_PORTS-1:0];
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l2_data_request_t data_requests_in[L2_NUM_PORTS-1:0];
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logic advance;
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l2_request_t arb_request;
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@ -70,7 +71,7 @@ module l2_arbiter
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l2_data_attributes_t new_attr;
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l2_data_attributes_t current_attr;
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logic [31:0] input_data [L2_NUM_PORTS-1:0];
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l2_data_request_t input_data [L2_NUM_PORTS-1:0];
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l2_mem_return_data_t mem_return_data;
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l2_return_data_t return_data [L2_NUM_PORTS-1:0];
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@ -93,11 +94,10 @@ module l2_arbiter
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//Repack input attributes
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assign requests_in[i].addr = request[i].addr;
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assign requests_in[i].be = request[i].be;
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assign requests_in[i].rnw = request[i].rnw;
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assign requests_in[i].is_amo = request[i].is_amo;
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assign requests_in[i].amo_type_or_burst_size = request[i].amo_type_or_burst_size;
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assign requests_in[i].sub_id = request[i].sub_id;
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assign requests_in[i].rnw = request[i].rnw;
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assign requests_in[i].is_amo = request[i].is_amo;
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assign requests_in[i].amo_type_or_burst_size = request[i].amo_type_or_burst_size;
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assign requests_in[i].sub_id = request[i].sub_id;
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assign input_fifos[i].data_in = requests_in[i];
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assign input_fifos[i].pop = input_fifos[i].valid & arb.grantee_v[i] & ~mem_addr_fifo.full;
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@ -121,12 +121,14 @@ module l2_arbiter
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assign input_data_fifos[i].push = request[i].wr_data_push;
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assign input_data_fifos[i].potential_push = request[i].wr_data_push;
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assign input_data_fifos[i].data_in = request[i].wr_data;
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assign data_requests_in[i].data = request[i].wr_data;
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assign data_requests_in[i].be = request[i].wr_data_be;
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assign input_data_fifos[i].data_in = data_requests_in[i];
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assign request[i].data_full = input_data_fifos[i].full;
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//FIFO instantiation
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cva5_fifo #(.DATA_WIDTH(32), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_data_fifo (.*, .fifo(input_data_fifos[i]));
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cva5_fifo #(.DATA_WIDTH($bits(l2_data_request_t)), .FIFO_DEPTH(L2_INPUT_FIFO_DEPTHS)) input_data_fifo (.*, .fifo(input_data_fifos[i]));
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//Arbiter FIFO side
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assign input_data_fifos[i].pop = (data_attributes.valid && (current_attr.id == i) && ~mem_data_fifo.full);
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@ -152,7 +154,6 @@ module l2_arbiter
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assign arb_request = requests[arb.grantee_i];
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assign mem_request.addr = arb_request.addr;
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assign mem_request.be = arb_request.be;
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assign mem_request.rnw = arb_request.rnw;
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assign mem_request.is_amo = arb_request.is_amo;
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assign mem_request.amo_type_or_burst_size = arb_request.amo_type_or_burst_size;
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@ -162,11 +163,10 @@ module l2_arbiter
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//unpack memory request attributes
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assign mem_addr_fifo_data_out = mem_addr_fifo.data_out;
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assign mem.addr = mem_addr_fifo_data_out.addr;
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assign mem.rnw = mem_addr_fifo_data_out.rnw;
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assign mem.be = mem_addr_fifo_data_out.be;
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assign mem.is_amo = mem_addr_fifo_data_out.is_amo;
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assign mem.amo_type_or_burst_size = mem_addr_fifo_data_out.amo_type_or_burst_size;
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assign mem.addr = mem_addr_fifo_data_out.addr;
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assign mem.rnw = mem_addr_fifo_data_out.rnw;
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assign mem.is_amo = mem_addr_fifo_data_out.is_amo;
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assign mem.amo_type_or_burst_size = mem_addr_fifo_data_out.amo_type_or_burst_size;
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assign mem.id = mem_addr_fifo_data_out.id;
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cva5_fifo #(.DATA_WIDTH($bits(l2_mem_request_t)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) input_fifo (.*, .fifo(mem_addr_fifo));
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@ -261,14 +261,17 @@ module l2_arbiter
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assign write_done = data_attributes.valid & ~mem_data_fifo.full & (burst_count == current_attr.burst_size);
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cva5_fifo #(.DATA_WIDTH($bits(32)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) mem_data (.*, .fifo(mem_data_fifo));
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cva5_fifo #(.DATA_WIDTH($bits(l2_data_request_t)), .FIFO_DEPTH(L2_MEM_ADDR_FIFO_DEPTH)) mem_data (.*, .fifo(mem_data_fifo));
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assign mem_data_fifo.push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort_request;
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assign mem_data_fifo.potential_push = data_attributes.valid & ~mem_data_fifo.full & ~current_attr.abort_request;
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assign mem_data_fifo.data_in = input_data[current_attr.id];
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assign mem.wr_data = mem_data_fifo.data_out;
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l2_data_request_t mem_data_request;
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assign mem_data_request = mem_data_fifo.data_out;
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assign mem.wr_data = mem_data_request.data;
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assign mem.wr_data_be = mem_data_request.be;
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assign mem.wr_data_valid = mem_data_fifo.valid;
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assign mem_data_fifo.pop = mem.wr_data_read;
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@ -306,4 +309,4 @@ module l2_arbiter
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end
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endgenerate
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endmodule
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endmodule
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@ -48,13 +48,17 @@ package l2_config_and_types;
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typedef struct packed{
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logic [29:0] addr;
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logic [3:0] be;
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logic rnw;
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logic is_amo;
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logic [4:0] amo_type_or_burst_size;
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logic [L2_SUB_ID_W-1:0] sub_id;
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} l2_request_t;
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typedef struct packed{
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logic [31:0] data;
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logic [3:0] be;
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} l2_data_request_t;
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typedef struct packed{
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logic [29:0] addr;
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logic [3:0] be;
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@ -25,7 +25,6 @@ interface l2_requester_interface;
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//l2_request_t request;
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logic [29:0] addr;
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logic [3:0] be;
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logic rnw;
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logic is_amo;
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logic [4:0] amo_type_or_burst_size;
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@ -42,6 +41,7 @@ interface l2_requester_interface;
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logic con_valid;
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logic [31:0] wr_data;
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logic [3:0] wr_data_be;
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logic wr_data_push;
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logic data_full;
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@ -50,26 +50,26 @@ interface l2_requester_interface;
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logic rd_data_valid;
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logic rd_data_ack;
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modport master (output addr, be, rnw, is_amo, amo_type_or_burst_size, sub_id,
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modport master (output addr, rnw, is_amo, amo_type_or_burst_size, sub_id,
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output request_push, input request_full,
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input inv_addr, inv_valid, output inv_ack,
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input con_result, con_valid,
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output wr_data, wr_data_push, input data_full,
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output wr_data, wr_data_be, wr_data_push, input data_full,
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input rd_data, rd_sub_id, rd_data_valid, output rd_data_ack);
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modport slave (input addr, be, rnw, is_amo, amo_type_or_burst_size, sub_id,
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modport slave (input addr, rnw, is_amo, amo_type_or_burst_size, sub_id,
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input request_push, output request_full,
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output inv_addr, inv_valid, input inv_ack,
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output con_result, con_valid,
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input wr_data, wr_data_push, output data_full,
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input wr_data, wr_data_be, wr_data_push, output data_full,
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output rd_data, rd_sub_id, rd_data_valid, input rd_data_ack);
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`ifdef __CVA5_FORMAL__
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modport formal (input addr, be, rnw, is_amo, amo_type_or_burst_size, sub_id,
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modport formal (input addr, rnw, is_amo, amo_type_or_burst_size, sub_id,
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request_push, output request_full,
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inv_addr, inv_valid, input inv_ack,
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con_result, con_valid,
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wr_data, wr_data_push, output data_full,
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wr_data, wr_data_be, wr_data_push, output data_full,
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rd_data, rd_sub_id, rd_data_valid, input rd_data_ack);
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`endif
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@ -81,7 +81,6 @@ interface l2_memory_interface;
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localparam L2_ID_W = $clog2(L2_NUM_PORTS) + L2_SUB_ID_W;
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logic [29:0] addr;
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logic [3:0] be;
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logic rnw;
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logic is_amo;
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logic [4:0] amo_type_or_burst_size;
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@ -93,6 +92,7 @@ interface l2_memory_interface;
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logic abort_request;
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logic [31:0] wr_data;
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logic [3:0] wr_data_be;
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logic wr_data_valid;
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logic wr_data_read;
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@ -100,20 +100,20 @@ interface l2_memory_interface;
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logic [L2_ID_W-1:0] rd_id;
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logic rd_data_valid;
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modport master (output addr, be, rnw, is_amo, amo_type_or_burst_size, id,
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modport master (output addr, rnw, is_amo, amo_type_or_burst_size, id,
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output request_valid, abort_request, input request_pop,
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output wr_data, wr_data_valid, input wr_data_read,
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output wr_data, wr_data_be, wr_data_valid, input wr_data_read,
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input rd_data, rd_id, rd_data_valid);
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modport slave (input addr, be, rnw, is_amo, amo_type_or_burst_size, id,
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modport slave (input addr, rnw, is_amo, amo_type_or_burst_size, id,
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input request_valid, abort_request, output request_pop,
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input wr_data, wr_data_valid, output wr_data_read,
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input wr_data, wr_data_be, wr_data_valid, output wr_data_read,
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output rd_data, rd_id, rd_data_valid);
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`ifdef __CVA5_FORMAL__
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modport formal (input addr, be, rnw, is_amo, amo_type_or_burst_size, id,
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modport formal (input addr, rnw, is_amo, amo_type_or_burst_size, id,
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request_valid, abort_request, output request_pop,
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wr_data, wr_data_valid, output wr_data_read,
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wr_data, wr_data_be, wr_data_valid, output wr_data_read,
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rd_data, rd_id, rd_data_valid);
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`endif
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@ -17,6 +17,10 @@ struct l2_arb_inputs{
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uint32_t sub_id;
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uint32_t be;
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};
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struct l2_data_inputs{
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uint32_t data;
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uint32_t be;
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};
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struct l2_arb_expected_output{
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uint32_t rd_data;
|
||||
uint32_t rd_sub_id;
|
||||
|
|
@ -24,7 +28,7 @@ struct l2_arb_expected_output{
|
|||
|
||||
queue<l2_arb_inputs> test_inputs;
|
||||
queue<l2_arb_expected_output> test_expected_output;
|
||||
queue<uint32_t> test_data_inputs;
|
||||
queue<l2_data_inputs> test_data_inputs;
|
||||
|
||||
void assign_read_input(uint32_t address, uint32_t burst_length, uint32_t sub_id){
|
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l2_arb_inputs in_elem{address, 1, burst_length, sub_id};
|
||||
|
|
@ -32,17 +36,19 @@ void assign_read_input(uint32_t address, uint32_t burst_length, uint32_t sub_id)
|
|||
};
|
||||
|
||||
void assign_write_input(uint32_t address, uint32_t burst_length, uint32_t sub_id, uint32_t be){
|
||||
l2_arb_inputs in_elem{address, 0, burst_length, sub_id, be};
|
||||
l2_arb_inputs in_elem{address, 0, burst_length, sub_id};
|
||||
test_inputs.push(in_elem);
|
||||
for(int i = burst_length-1 ; i >= 0; i--){
|
||||
test_data_inputs.push(i+71);
|
||||
l2_data_inputs in_data_elem{i+71, be};
|
||||
test_data_inputs.push(in_data_elem);
|
||||
}
|
||||
};
|
||||
|
||||
void assign_single_write_input(uint32_t address, uint32_t sub_id, uint32_t data, uint32_t be){
|
||||
l2_arb_inputs in_elem{address, 0, 1, sub_id, be};
|
||||
l2_arb_inputs in_elem{address, 0, 1, sub_id};
|
||||
test_inputs.push(in_elem);
|
||||
test_data_inputs.push(data);
|
||||
l2_data_inputs in_data_elem{data, be};
|
||||
test_data_inputs.push(in_data_elem);
|
||||
|
||||
};
|
||||
vluint64_t main_time = 0; // Current simulation time
|
||||
|
|
@ -142,7 +148,6 @@ int main(int argc, char **argv) {
|
|||
tb->is_amo = 0;
|
||||
tb->amo_type_or_burst_size = elem.burst_length - 1;
|
||||
tb->sub_id = elem.sub_id;
|
||||
tb->be = elem.be;
|
||||
number_of_data_left = elem.burst_length;
|
||||
tb->request_push = 1;
|
||||
tb->wr_data_push = 0;
|
||||
|
|
@ -151,9 +156,10 @@ int main(int argc, char **argv) {
|
|||
tb->request_push = 0;
|
||||
|
||||
if(!tb->data_full){
|
||||
uint32_t data = test_data_inputs.front();
|
||||
l2_data_inputs data_elem = test_data_inputs.front();
|
||||
test_data_inputs.pop();
|
||||
tb->wr_data = data;
|
||||
tb->wr_data = data_elem.data;
|
||||
tb->wr_data_be = data_elem.be;
|
||||
tb->wr_data_push = 1;
|
||||
|
||||
number_of_data_left--;
|
||||
|
|
|
|||
|
|
@ -77,7 +77,6 @@ module axi_l2_test # (
|
|||
|
||||
//L2 interface
|
||||
input logic [29:0] addr,
|
||||
input logic [3:0] be,
|
||||
input logic rnw,
|
||||
input logic is_amo,
|
||||
input logic [4:0] amo_type_or_burst_size,
|
||||
|
|
@ -94,6 +93,7 @@ module axi_l2_test # (
|
|||
output logic con_valid,
|
||||
|
||||
input logic [31:0] wr_data,
|
||||
input logic [3:0] wr_data_be,
|
||||
input logic wr_data_push,
|
||||
output logic data_full,
|
||||
|
||||
|
|
@ -224,7 +224,6 @@ module axi_l2_test # (
|
|||
// assign m_axi.bresp = bus_axi_bresp;
|
||||
|
||||
assign l2[0].addr = addr;
|
||||
assign l2[0].be = be;
|
||||
assign l2[0].rnw = rnw;
|
||||
assign l2[0].is_amo = is_amo;
|
||||
assign l2[0].amo_type_or_burst_size = amo_type_or_burst_size;
|
||||
|
|
@ -241,6 +240,7 @@ module axi_l2_test # (
|
|||
assign con_valid = l2[0].con_valid;
|
||||
|
||||
assign l2[0].wr_data = wr_data;
|
||||
assign l2[0].wr_data_be = wr_data_be;
|
||||
assign l2[0].wr_data_push = wr_data_push;
|
||||
assign data_full = l2[0].data_full;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue