github-mirrors/cva5
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva5.git synced 2025-04-22 13:07:33 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

moved reg bank select to issue stage

Browse source
This commit is contained in:
Eric Matthews 2020-09-28 18:24:24 -07:00
parent 6d5203f4c8
commit f08ebf5786
3 changed files with 16 additions and 20 deletions
Download patch file Download diff file Expand all files Collapse all files

3
core/decode_and_issue.sv
View file

@ -59,6 +59,7 @@ module decode_and_issue (
input logic rs_id_inuse [REGFILE_READ_PORTS],
output logic instruction_issued,
output logic instruction_issued_with_rd,
output logic illegal_instruction,
//Trace signals
@ -218,7 +219,7 @@ module decode_and_issue (
assign issue_to = {NUM_UNITS{issue_valid}} & unit_operands_ready & issue_ready;
assign instruction_issued = issue_valid & |(unit_operands_ready & issue_ready);
assign instruction_issued_with_rd = instruction_issued & issue.uses_rd;
////////////////////////////////////////////////////
//ALU unit inputs
logic [XLEN-1:0] alu_rs1_data;

30
core/register_file_and_writeback.sv
View file

@ -30,6 +30,7 @@ module register_file_and_writeback
//Issue interface
input issue_packet_t issue,
input logic instruction_issued_with_rd,
input logic alu_issued,
output logic [31:0] rs_data [REGFILE_READ_PORTS],
//ID Metadata
@ -131,7 +132,7 @@ module register_file_and_writeback
.clk, .rst,
.rd_addr(retired_rd_addr[i]),
.new_data(retiring_data[i]),
.commit(update_lvt[i] & (|retired_rd_addr[i])),
.commit(retired[i] & (|retired_rd_addr[i])),
.read_addr(issue.rs_addr),
.data(rs_data_set[i])
);
@ -139,25 +140,16 @@ module register_file_and_writeback
////////////////////////////////////////////////////
//Register File LVT
//Only update lvt if the retiring instrucion is the most recently issued
//write to a given register. This check allows multiple oustanding writes
//to the same register. As instructions can complete out-of-order, only
//the most recently issued write to any given register will be committed
logic update_lvt [COMMIT_PORTS];
always_comb begin
update_lvt[0] = retired[0];// & (alu_selected ? alu_issued : (id_for_rd[0] == ids_retiring[0]));
for (int i = 1; i < COMMIT_PORTS; i++)
update_lvt[i] = retired[i] & (id_for_rd[i] == ids_retiring[i]) & ~(retired[0] & retired_rd_addr[0] == retired_rd_addr[i]);
logic [$clog2(COMMIT_PORTS)-1:0] bank_sel [32];
always_ff @ (posedge clk) begin
if (instruction_issued_with_rd)
bank_sel[issue.rd_addr] <= ~alu_issued;
end
always_comb begin
for (int i = 0; i < REGFILE_READ_PORTS; i++) begin
rs_sel[i] = bank_sel[issue.rs_addr[i]];
end
end
regfile_bank_sel regfile_lvt (
.clk, .rst,
.rs_addr(issue.rs_addr),
.rs_sel,
.rd_addr(retired_rd_addr),
.rd_retired(update_lvt)
);
////////////////////////////////////////////////////
//Register File Muxing

3
core/taiga.sv
View file

@ -136,6 +136,7 @@ module taiga (
//Decode Unit and Fetch Unit
logic illegal_instruction;
logic instruction_issued;
logic instruction_issued_with_rd;
logic gc_flush_required;
//LS
@ -349,6 +350,7 @@ module taiga (
.rs_id (rs_id),
.rs_id_inuse (rs_id_inuse),
.instruction_issued (instruction_issued),
.instruction_issued_with_rd (instruction_issued_with_rd),
.illegal_instruction (illegal_instruction),
.tr_operand_stall (tr_operand_stall),
.tr_unit_stall (tr_unit_stall),
@ -377,6 +379,7 @@ module taiga (
.clk (clk),
.rst (rst),
.issue (issue),
.instruction_issued_with_rd (instruction_issued_with_rd),
.alu_issued (alu_issued),
.rs_data (rs_data),
.ids_retiring (ids_retiring),