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Update uses of l2_requester_interface::be

Browse source 
-> examples/litex/l1_to_wishbone.sv
-> test_benches/verilator/AXI_DDR_simulation/axi_l2_text.sv, .cc

Signed-off-by: Florian Meisel <meisel@esa.tu-darmstadt.de>
This commit is contained in:
Florian Meisel 2022-09-08 20:01:26 +02:00
parent 6b1d2280d8
commit f6a593402a
3 changed files with 32 additions and 20 deletions
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26
examples/litex/l1_to_wishbone.sv
View file

@ -38,11 +38,14 @@ module l1_to_wishbone
localparam MAX_REQUESTS = 32;
fifo_interface #(.DATA_WIDTH($bits(l2_request_t))) request_fifo ();
fifo_interface #(.DATA_WIDTH(32)) data_fifo ();
fifo_interface #(.DATA_WIDTH($bits(l2_data_request_t))) data_fifo ();
l2_request_t request_in;
l2_request_t request;
l2_data_request_t data_request_in;
l2_data_request_t data_request;
logic request_complete;
////////////////////////////////////////////////////
//Implementation
@ -51,11 +54,10 @@ module l1_to_wishbone
//Repack input attributes
assign request_in.addr = cpu.addr;
assign request_in.be = cpu.be;
assign request_in.rnw = cpu.rnw;
assign request_in.is_amo = cpu.is_amo;
assign request_in.amo_type_or_burst_size = cpu.amo_type_or_burst_size;
assign request_in.sub_id = cpu.sub_id;
assign request_in.rnw = cpu.rnw;
assign request_in.is_amo = cpu.is_amo;
assign request_in.amo_type_or_burst_size = cpu.amo_type_or_burst_size;
assign request_in.sub_id = cpu.sub_id;
assign request_fifo.push = cpu.request_push;
assign request_fifo.potential_push = cpu.request_push;
@ -63,10 +65,14 @@ module l1_to_wishbone
assign request_fifo.data_in = request_in;
assign request = request_fifo.data_out;
assign data_request_in.data = cpu.wr_data;
assign data_request_in.be = cpu.wr_data_be;
assign data_fifo.push = cpu.wr_data_push;
assign data_fifo.potential_push = cpu.wr_data_push;
assign data_fifo.pop = wishbone.we & wishbone.ack;
assign data_fifo.data_in = cpu.wr_data;
assign data_fifo.data_in = data_request_in;
assign data_request = data_fifo.data_out;
cva5_fifo #(.DATA_WIDTH($bits(l2_request_t)), .FIFO_DEPTH(MAX_REQUESTS))
request_fifo_block (
@ -74,7 +80,7 @@ module l1_to_wishbone
.rst (rst),
.fifo (request_fifo)
);
cva5_fifo #(.DATA_WIDTH(32), .FIFO_DEPTH(MAX_REQUESTS))
cva5_fifo #(.DATA_WIDTH($bits(l2_data_request_t)), .FIFO_DEPTH(MAX_REQUESTS))
data_fifo_block (
.clk (clk),
.rst (rst),
@ -100,10 +106,10 @@ module l1_to_wishbone
assign wishbone.adr[29:5] = request.addr[29:5];
assign wishbone.adr[4:0] = (request.addr[4:0] & ~burst_size) | (burst_count & burst_size);
assign wishbone.sel = request.rnw ? '1 : request.be;
assign wishbone.sel = request.rnw ? '1 : data_request.be;
assign wishbone.we = ~request.rnw;
assign wishbone.dat_w = data_fifo.data_out;
assign wishbone.dat_w = data_request.data;
assign wishbone.stb = request_fifo.valid;
assign wishbone.cyc = request_fifo.valid;

22
test_benches/verilator/AXI_DDR_simulation/axi_l2_test.cc
View file

@ -17,6 +17,10 @@ struct l2_arb_inputs{
uint32_t sub_id;
uint32_t be;
};
struct l2_data_inputs{
uint32_t data;
uint32_t be;
};
struct l2_arb_expected_output{
uint32_t rd_data;
uint32_t rd_sub_id;
@ -24,7 +28,7 @@ struct l2_arb_expected_output{
queue<l2_arb_inputs> test_inputs;
queue<l2_arb_expected_output> test_expected_output;
queue<uint32_t> test_data_inputs;
queue<l2_data_inputs> test_data_inputs;
void assign_read_input(uint32_t address, uint32_t burst_length, uint32_t sub_id){
l2_arb_inputs in_elem{address, 1, burst_length, sub_id};
@ -32,17 +36,19 @@ void assign_read_input(uint32_t address, uint32_t burst_length, uint32_t sub_id)
};
void assign_write_input(uint32_t address, uint32_t burst_length, uint32_t sub_id, uint32_t be){
l2_arb_inputs in_elem{address, 0, burst_length, sub_id, be};
l2_arb_inputs in_elem{address, 0, burst_length, sub_id};
test_inputs.push(in_elem);
for(int i = burst_length-1 ; i >= 0; i--){
test_data_inputs.push(i+71);
l2_data_inputs in_data_elem{i+71, be};
test_data_inputs.push(in_data_elem);
}
};
void assign_single_write_input(uint32_t address, uint32_t sub_id, uint32_t data, uint32_t be){
l2_arb_inputs in_elem{address, 0, 1, sub_id, be};
l2_arb_inputs in_elem{address, 0, 1, sub_id};
test_inputs.push(in_elem);
test_data_inputs.push(data);
l2_data_inputs in_data_elem{data, be};
test_data_inputs.push(in_data_elem);
};
vluint64_t main_time = 0; // Current simulation time
@ -142,7 +148,6 @@ int main(int argc, char **argv) {
tb->is_amo = 0;
tb->amo_type_or_burst_size = elem.burst_length - 1;
tb->sub_id = elem.sub_id;
tb->be = elem.be;
number_of_data_left = elem.burst_length;
tb->request_push = 1;
tb->wr_data_push = 0;
@ -151,9 +156,10 @@ int main(int argc, char **argv) {
tb->request_push = 0;
if(!tb->data_full){
uint32_t data = test_data_inputs.front();
l2_data_inputs data_elem = test_data_inputs.front();
test_data_inputs.pop();
tb->wr_data = data;
tb->wr_data = data_elem.data;
tb->wr_data_be = data_elem.be;
tb->wr_data_push = 1;
number_of_data_left--;

4
test_benches/verilator/AXI_DDR_simulation/axi_l2_test.sv
View file

@ -77,7 +77,6 @@ module axi_l2_test # (
//L2 interface
input logic [29:0] addr,
input logic [3:0] be,
input logic rnw,
input logic is_amo,
input logic [4:0] amo_type_or_burst_size,
@ -94,6 +93,7 @@ module axi_l2_test # (
output logic con_valid,
input logic [31:0] wr_data,
input logic [3:0] wr_data_be,
input logic wr_data_push,
output logic data_full,
@ -224,7 +224,6 @@ module axi_l2_test # (
// assign m_axi.bresp = bus_axi_bresp;
assign l2[0].addr = addr;
assign l2[0].be = be;
assign l2[0].rnw = rnw;
assign l2[0].is_amo = is_amo;
assign l2[0].amo_type_or_burst_size = amo_type_or_burst_size;
@ -241,6 +240,7 @@ module axi_l2_test # (
assign con_valid = l2[0].con_valid;
assign l2[0].wr_data = wr_data;
assign l2[0].wr_data_be = wr_data_be;
assign l2[0].wr_data_push = wr_data_push;
assign data_full = l2[0].data_full;