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port order fix

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This commit is contained in:
Eric Matthews 2020-10-30 17:37:02 +00:00
parent e8cd051c40
commit f949dc1154
1 changed files with 1 additions and 1 deletions
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core/taiga.sv
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@ -68,7 +68,7 @@ module taiga (
div_inputs_t div_inputs;
gc_inputs_t gc_inputs;
unit_issue_interface unit_issue [NUM_UNITS]();
unit_issue_interface unit_issue [NUM_UNITS-1:0]();
logic alu_issued;
exception_packet_t ls_exception;