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Added unit TB for DIV and MUL
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274
test_benches/div_unit_tb.sv
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274
test_benches/div_unit_tb.sv
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/*
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* Copyright © 2017 Eric Matthews, Lesley Shannon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Eric Matthews <ematthew@sfu.ca>
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*/
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`timescale 1ns / 1ps
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import taiga_config::*;
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import taiga_types::*;
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module div_unit_tb ( );
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//DUT Regs and Wires
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logic clk;
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logic rst;
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func_unit_ex_interface div_ex();
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unit_writeback_interface div_wb();
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div_inputs_t div_inputs;
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//Internal Regs and Wires
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integer test_number;
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//Input
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integer rs1_rand;
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integer rs2_rand;
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int unsigned rs1_urand;
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int unsigned rs2_urand;
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integer result_rand;
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logic [ 1: 0] op_rand;
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logic reuse_rand;
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//Result
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logic [31: 0] result_queue[$];
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logic [31: 0] temp_result;
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//Latency
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parameter MAX_RESPONSE_LATENCY = 32'hF;
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logic wb_done;
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logic firstPop;
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logic [31: 0] latency_queue[$];
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logic [31: 0] wb_done_acc;
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logic [31: 0] response_latency;
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//DUT
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div_unit uut (.*);
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//Reset
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task reset;
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begin
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rst = 1'b1;
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#100 rst = 1'b0;
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end
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endtask
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//Clock Gen
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always
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#1 clk = ~clk;
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//Latency Logic
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function int genRandLatency();
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genRandLatency = $random & MAX_RESPONSE_LATENCY;
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endfunction
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always_ff @(posedge clk) begin
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if (rst) begin
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wb_done_acc <= 32'h1;
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firstPop <= 1'b1;
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response_latency <= 32'hFFFFFFFF;
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end else begin
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if (div_wb.done) begin
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wb_done_acc <= wb_done_acc + 1;
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end else begin
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wb_done_acc <= 32'h1;
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end
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if (firstPop | div_wb.accepted) begin
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response_latency <= latency_queue.pop_front();
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firstPop <= 1'b0;
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end else begin
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response_latency <= response_latency;
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end
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end
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end
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assign wb_done = div_wb.done & (wb_done_acc >= response_latency);
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always_ff @(posedge clk) begin
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if (rst)
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div_wb.accepted <= 0;
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else
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div_wb.accepted <= wb_done;
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end
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//Output checker
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always_ff @(posedge clk) begin
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if (rst)
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test_number <= 1;
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if (div_wb.accepted) begin
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test_number <= test_number + 1;
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temp_result = result_queue.pop_front();
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assert (div_wb.rd == temp_result) else $error("Incorrect result on test number %d. (%d, should be: %d)", test_number, div_wb.rd, temp_result);
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end
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end
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//Driver
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task test_div (input integer a, b, result, latency, logic[1:0] op, logic reuse);
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wait (~clk & div_ex.ready);
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div_inputs.rs1 = a;
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div_inputs.rs2 = b;
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div_inputs.op = op;
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div_inputs.div_zero = (div_inputs.rs2 == 0);
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div_inputs.reuse_result = reuse;
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result_queue.push_back(result);
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latency_queue.push_back(latency);
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div_ex.new_request_dec = 1; #2
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div_ex.new_request_dec = 0;
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endtask
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//Generator + Transaction
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task test_gen();
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op_rand = $urandom % 4;
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rs1_rand = $random;
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rs2_rand = $random;
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reuse_rand = 0;
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//SW model
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case (op_rand)
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2'b00:begin //Div
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if (rs2_rand == 0) begin
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result_rand = -1;
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end else begin
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result_rand = rs1_rand / rs2_rand;
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end
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end
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2'b01:begin //uDiv
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if (rs2_rand == 0) begin
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result_rand = -1;
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end else begin
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rs1_urand = rs1_rand;
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rs2_urand = rs2_rand;
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result_rand = rs1_urand / rs2_urand;
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end
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end
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2'b10:begin //Rem
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if (rs2_rand == 0) begin
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result_rand = rs1_rand;
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end else begin
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result_rand = rs1_rand % rs2_rand;
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end
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end
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2'b11:begin //uRem
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if (rs2_rand == 0) begin
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result_rand = rs1_rand;
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end else begin
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rs1_urand = rs1_rand;
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rs2_urand = rs2_rand;
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result_rand = rs1_urand % rs2_urand;
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end
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end
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endcase
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test_div (rs1_rand, rs2_rand, result_rand, genRandLatency(), op_rand, reuse_rand);
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endtask
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initial
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begin
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clk = 0;
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rst = 1;
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div_inputs.rs1 = 0;
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div_inputs.rs2 = 0;
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div_inputs.op = 0;
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div_inputs.reuse_result = 0;
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div_ex.new_request_dec = 0;
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div_inputs.div_zero = 0;
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div_wb.accepted = 0;
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reset();
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//Randomized Test (operation + latency)
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for (int i=0; i < 1000; i = i+1) begin
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test_gen();
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end
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for (int i=0; i < 6; i = i+5) begin
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//Div test
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test_div( 20, 6, 3, i, 2'b00, 0);
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test_div(-20, -3, 6, i, 2'b00, 0);
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test_div(-20, 6, -3, i, 2'b00, 0);
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test_div( 20, -6, -3, i, 2'b00, 0);
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test_div(-20, -6, 3, i, 2'b00, 0);
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test_div(-1<<31, 1, -1<<31, i, 2'b00, 0);
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test_div(-1<<31, -1, -1<<31, i, 2'b00, 0);
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test_div(-1<<31, 0, -1, i, 2'b00, 0);
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test_div(-1, 0, -1, i, 2'b00, 0);
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test_div(0, 0, -1, i, 2'b00, 0);
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//uDiv test
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test_div( 20, 6, 3, i, 2'b01, 0);
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test_div(-20, 6, 715827879, i, 2'b01, 0);
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test_div( 20, -6, 0, i, 2'b01, 0);
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test_div(-20, -6, 0, i, 2'b01, 0);
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test_div(-1<<31, 1, -1<<31, i, 2'b01, 0);
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test_div(-1<<31, -1, 0, i, 2'b01, 0);
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test_div(-1<<31, 0, -1, i, 2'b01, 0);
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test_div( 1, 0, -1, i, 2'b01, 0);
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test_div( 0, 0, -1, i, 2'b01, 0);
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test_div(486456, 1, 486456, i, 2'b01, 0);
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test_div( 200, 200, 1, i, 2'b01, 0);
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test_div(234678, 2, 234678/2, i, 2'b01, 0);
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//rem test
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test_div( 20, 6, 2, i, 2'b10, 0);
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test_div(-20, 6, -2, i, 2'b10, 0);
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test_div( 20, -6, 2, i, 2'b10, 0);
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test_div(-20, -6, -2, i, 2'b10, 0);
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test_div(-1<<31, 1, 0, i, 2'b10, 0);
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test_div(-1<<31, -1, 0, i, 2'b10, 0);
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test_div(-1<<31, 0, -1<<31, i, 2'b10, 0);
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test_div( 1, 0, 1, i, 2'b10, 0);
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test_div( 0, 0, 0, i, 2'b10, 0);
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//remu test
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test_div( 20, 6, 2, i, 2'b11, 0);
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test_div(-20, 6, 2, i, 2'b11, 0);
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test_div( 20, -6, 20, i, 2'b11, 0);
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test_div(-20, -6, -20, i, 2'b11, 0);
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test_div(-1<<31, 1, 0, i, 2'b11, 0);
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test_div(-1<<31, -1, -1<<31, i, 2'b11, 0);
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test_div(-1<<31, 0, -1<<31, i, 2'b11, 0);
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test_div( 1, 0, 1, i, 2'b11, 0);
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test_div( 0, 0, 0, i, 2'b11, 0);
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//reuse result tests
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test_div(20, 6, 2, i, 2'b11, 0);
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test_div(20, 6, 2, i, 2'b10, 1);
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test_div(20, 6, 3, i, 2'b00, 1);
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test_div(200, 200, 1, i, 2'b01, 0);
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test_div(200, 200, 1, i, 2'b00, 1);
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end
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wait (result_queue.size() == 0);
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wait (latency_queue.size() == 0);
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#200;
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if (result_queue.size() == 0) begin
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// $display("queue size: %d", result_queue.size());
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$display("Div Unit Test -------------------- Passed");
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end
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$finish;
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end
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endmodule
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274
test_benches/mul_unit_tb.sv
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274
test_benches/mul_unit_tb.sv
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@ -0,0 +1,274 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 05/14/2018 02:55:10 PM
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// Design Name:
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// Module Name: mul_unit_tb
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// Project Name: taiga
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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import taiga_config::*;
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import taiga_types::*;
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module mul_unit_tb();
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//DUT Regs and Wires
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logic clk;
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logic rst;
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func_unit_ex_interface mul_ex();
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unit_writeback_interface mul_wb();
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mul_inputs_t mul_inputs;
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//Internal Regs and Wires
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integer test_number;
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//Input
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int rs1_rand;
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int rs2_rand;
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int unsigned rs1_urand;
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int unsigned rs2_urand;
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longint signedMulResult;
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longint unsigned unsignedMulResult;
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logic [31: 0] result_rand;
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logic [ 1: 0] op_rand;
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//Result
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logic [31: 0] result_queue[$];
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logic [31: 0] temp_result;
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//Latency
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parameter MAX_RESPONSE_LATENCY = 32'hF;
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logic wb_done;
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logic firstPop;
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logic [31: 0] latency_queue[$];
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logic [31: 0] wb_done_acc;
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logic [31: 0] response_latency;
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//DUT
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mul_unit uut (.*);
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//Reset
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task reset;
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begin
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rst = 1'b1;
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#100 rst = 1'b0;
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end
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endtask
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//Clock Gen
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always
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#1 clk = ~clk;
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//Latency Logic
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function int genRandLatency();
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genRandLatency = $random & MAX_RESPONSE_LATENCY;
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endfunction
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always_ff @(posedge clk) begin
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if (rst) begin
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wb_done_acc <= 32'h1;
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firstPop <= 1'b1;
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response_latency <= 32'hFFFFFFFF;
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end else begin
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if (mul_wb.done) begin
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wb_done_acc <= wb_done_acc + 1;
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end else begin
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wb_done_acc <= 32'h1;
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end
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if (firstPop | mul_wb.accepted) begin
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response_latency <= latency_queue.pop_front();
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firstPop <= 1'b0;
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end else begin
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response_latency <= response_latency;
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end
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end
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end
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assign wb_done = mul_wb.done & (wb_done_acc >= response_latency);
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always_ff @(posedge clk) begin
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if (rst)
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mul_wb.accepted <= 0;
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else
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mul_wb.accepted <= wb_done;
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end
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//Output checker
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always_ff @(posedge clk) begin
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if (rst)
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test_number <= 1;
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if (mul_wb.accepted) begin
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test_number <= test_number + 1;
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temp_result = result_queue.pop_front();
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assert (mul_wb.rd == temp_result) else $error("Incorrect result on test number %d. (%h, should be: %h)", test_number, mul_wb.rd, temp_result);
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end
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end
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//Driver
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task test_div (input logic [XLEN-1:0] a, b, result, latency, logic[1:0] op);
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wait (~clk & mul_ex.ready);
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mul_inputs.rs1 = a;
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mul_inputs.rs2 = b;
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mul_inputs.op = op;
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result_queue.push_back(result);
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latency_queue.push_back(latency);
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mul_ex.new_request_dec = 1; #2
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mul_ex.new_request_dec = 0;
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endtask
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//Generator + Transaction
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task test_gen();
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op_rand = $urandom % 4;
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rs1_rand = $random;
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rs2_rand = $random;
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//SW model
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case (op_rand)
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2'b00:begin //MUL
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signedMulResult = rs1_rand * rs2_rand;
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result_rand = signedMulResult[31: 0];
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end
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2'b01:begin //MULH
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signedMulResult = rs1_rand * rs2_rand;
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result_rand = signedMulResult[63:32];
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end
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2'b10:begin //MULHSU - rs1(signed) & rs2(unsigned)
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if (rs1_rand[31]) begin
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rs1_urand = rs1_rand * -1;
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rs2_urand = rs2_rand;
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unsignedMulResult = rs1_urand * rs2_urand;
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signedMulResult = unsignedMulResult;
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signedMulResult = signedMulResult * -1;
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result_rand = signedMulResult[63:32];
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end else begin
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rs1_urand = rs1_rand;
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rs2_urand = rs2_rand;
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unsignedMulResult = rs1_urand * rs2_urand;
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result_rand = unsignedMulResult[63:32];
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end
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end
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2'b11:begin //MULHU
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rs1_urand = rs1_rand;
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rs2_urand = rs2_rand;
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unsignedMulResult = rs1_urand * rs2_urand;
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result_rand = unsignedMulResult[63:32];
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end
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endcase
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test_div (rs1_rand, rs2_rand, result_rand, genRandLatency(), op_rand);
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endtask
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initial
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begin
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clk = 0;
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rst = 1;
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mul_inputs.rs1 = 0;
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mul_inputs.rs2 = 0;
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mul_inputs.op = 0;
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mul_ex.new_request_dec = 0;
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mul_wb.accepted = 0;
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reset();
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//Randomized Test (operation + latency)
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for (int i=0; i < 1000; i = i+1) begin
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test_gen();
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end
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for (int i=0; i < 6; i = i+5) begin
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//MUL
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test_div (32'h00007e00, 32'hb6db6db7, 32'h00001200, i, 2'b00);
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test_div (32'h00007fc0, 32'hb6db6db7, 32'h00001240, i, 2'b00);
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test_div (32'h00000000, 32'h00000000, 32'h00000000, i, 2'b00);
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test_div (32'h00000001, 32'h00000001, 32'h00000001, i, 2'b00);
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test_div (32'h00000003, 32'h00000007, 32'h00000015, i, 2'b00);
|
||||
|
||||
test_div (32'hffff8000, 32'h00000000, 32'h00000000, i, 2'b00);
|
||||
test_div (32'h00000000, 32'h80000000, 32'h00000000, i, 2'b00);
|
||||
test_div (32'hffff8000, 32'h80000000, 32'h00000000, i, 2'b00);
|
||||
|
||||
test_div (32'haaaaaaab, 32'h0002fe7d, 32'h0000ff7f, i, 2'b00);
|
||||
test_div (32'h0002fe7d, 32'haaaaaaab, 32'h0000ff7f, i, 2'b00);
|
||||
|
||||
test_div (32'hff000000, 32'hff000000, 32'h00000000, i, 2'b00);
|
||||
|
||||
test_div (32'hffffffff, 32'hffffffff, 32'h00000001, i, 2'b00);
|
||||
test_div (32'h00000001, 32'hffffffff, 32'hffffffff, i, 2'b00);
|
||||
test_div (32'hffffffff, 32'h00000001, 32'hffffffff, i, 2'b00);
|
||||
|
||||
//MULH
|
||||
test_div (32'h00000000, 32'h00000000, 32'h00000000, i, 2'b01);
|
||||
test_div (32'h00000001, 32'h00000001, 32'h00000000, i, 2'b01);
|
||||
test_div (32'h00000003, 32'h00000007, 32'h00000000, i, 2'b01);
|
||||
|
||||
test_div (32'h00000000, 32'hffff8000, 32'h00000000, i, 2'b01);
|
||||
test_div (32'h80000000, 32'h00000000, 32'h00000000, i, 2'b01);
|
||||
test_div (32'h80000000, 32'h00000000, 32'h00000000, i, 2'b01);
|
||||
|
||||
test_div (32'haaaaaaab, 32'h0002fe7d, 32'hffff0081, i, 2'b01);
|
||||
test_div (32'h0002fe7d, 32'haaaaaaab, 32'hffff0081, i, 2'b01);
|
||||
|
||||
test_div (32'hff000000, 32'hff000000, 32'h00010000, i, 2'b01);
|
||||
|
||||
test_div (32'hffffffff, 32'hffffffff, 32'h00000000, i, 2'b01);
|
||||
test_div (32'hffffffff, 32'h00000001, 32'hffffffff, i, 2'b01);
|
||||
test_div (32'h00000001, 32'hffffffff, 32'hffffffff, i, 2'b01);
|
||||
|
||||
//MULHSU - rs1(signed) & rs2(unsigned)
|
||||
test_div (32'h00000000, 32'h00000000, 32'h00000000, i, 2'b10);
|
||||
test_div (32'h00000001, 32'h00000001, 32'h00000000, i, 2'b10);
|
||||
test_div (32'h00000007, 32'h00000003, 32'h00000000, i, 2'b10);
|
||||
|
||||
test_div (32'hffff8000, 32'h00000000, 32'h00000000, i, 2'b10);
|
||||
test_div (32'h00000000, 32'h80000000, 32'h00000000, i, 2'b10);
|
||||
test_div (32'h80000000, 32'hffff8000, 32'h80004000, i, 2'b10);
|
||||
|
||||
test_div (32'haaaaaaab, 32'h0002fe7d, 32'hffff0081, i, 2'b10);
|
||||
test_div (32'h0002fe7d, 32'haaaaaaab, 32'h0001fefe, i, 2'b10);
|
||||
|
||||
test_div (32'hff000000, 32'hff000000, 32'hff010000, i, 2'b10);
|
||||
|
||||
test_div (32'hffffffff, 32'hffffffff, 32'hffffffff, i, 2'b10);
|
||||
test_div (32'hffffffff, 32'h00000001, 32'hffffffff, i, 2'b10);
|
||||
test_div (32'h00000001, 32'hffffffff, 32'h00000000, i, 2'b10);
|
||||
|
||||
//MULHU
|
||||
test_div (32'h00000000, 32'h00000000, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h00000001, 32'h00000001, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h00000003, 32'h00000007, 32'h00000000, i, 2'b11);
|
||||
|
||||
test_div (32'hffff8000, 32'h00000000, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h80000000, 32'h00000000, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h80000000, 32'hffff8000, 32'h7fffc000, i, 2'b11);
|
||||
|
||||
test_div (32'haaaaaaab, 32'h0002fe7d, 32'h0001fefe, i, 2'b11);
|
||||
test_div (32'h0002fe7d, 32'haaaaaaab, 32'h0001fefe, i, 2'b11);
|
||||
|
||||
test_div (32'hff000000, 32'hff000000, 32'hfe010000, i, 2'b11);
|
||||
|
||||
test_div (32'hffffffff, 32'hffffffff, 32'hfffffffe, i, 2'b11);
|
||||
test_div (32'hffffffff, 32'h00000001, 32'h00000000, i, 2'b11);
|
||||
test_div (32'h00000001, 32'hffffffff, 32'h00000000, i, 2'b11);
|
||||
end
|
||||
|
||||
wait (result_queue.size() == 0);
|
||||
wait (latency_queue.size() == 0);
|
||||
#200;
|
||||
if (result_queue.size() == 0) begin
|
||||
// $display("queue size: %d", result_queue.size());
|
||||
$display("Mul Unit Test -------------------- Passed");
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue