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Added missing import statement.

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This commit is contained in:
Zavier Aguila 2020-07-27 15:36:10 -07:00
parent 3c9178fb5f
commit ffacfa1fbc
1 changed files with 1 additions and 0 deletions
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core/xilinx/xilinx_byte_enable_ram.sv
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@ -22,6 +22,7 @@
import taiga_config::*;
import taiga_types::*;
import riscv_types::*;
module xilinx_byte_enable_ram #(
parameter LINES = 4096,