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102 lines
3.5 KiB
Makefile
102 lines
3.5 KiB
Makefile
###############################################################
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VERILATOR_DIR=$(CVA5_DIR)/test_benches/verilator
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# Sources for verilator
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CVA5_HW_SRCS = $(addprefix $(CVA5_DIR)/, $(shell cat $(CVA5_DIR)/tools/compile_order))
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CVA5_SIM_SRCS = $(addprefix $(VERILATOR_DIR)/, CVA5Tracer.cc SimMem.cc cva5_sim.cc AXI_DDR_simulation/axi_ddr_sim.cc AXI_DDR_simulation/ddr_page.cc)
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CVA5_INCLUDED_SIM_SRCS = $(addprefix $(VERILATOR_DIR)/, cva5_sim.cc AXI_DDR_simulation/ddr_page.cc SimMem.cc)
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#Tracing: Set to True or False
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TRACE_ENABLE?=False
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#Simulation Binary Name
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CVA5_SIM_DIR?=$(VERILATOR_DIR)/build
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CVA5_SIM?=$(CVA5_SIM_DIR)/cva5-sim
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#(to-do)DDR Pre-Initialization
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#LOAD_DDR_FROM_FILE = False
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#DDR_FILE = "\"path_to_DDR_init_file\""
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#DDR_FILE_STARTING_LOCATION = 0
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#DDR_FILE_NUM_BYTES = 0
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#AXI DDR Parameters
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DDR_SIZE_GB = 4
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PAGE_SIZE_KB = 2
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MAX_READ_REQ = 8
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MAX_WRITE_REQ = $(MAX_READ_REQ)
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MIN_RD_DELAY = 15
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MAX_RD_DELAY = 30
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MIN_WR_DELAY = 1
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MAX_WR_DELAY = 1
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DELAY_SEED = 867583
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######################################################################
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ddr_size_def = DDR_SIZE=\(long\)$(DDR_SIZE_GB)*\(long\)1073741824
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page_size_def = PAGE_SIZE=\($(PAGE_SIZE_KB)*1024\)
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max_inflight_read_requests = MAX_INFLIGHT_RD_REQ=$(MAX_READ_REQ)
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max_inflight_write_requests = MAX_INFLIGHT_WR_REQ=$(MAX_WRITE_REQ)
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mix_delay_read = MIN_DELAY_RD=$(MIN_RD_DELAY)
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max_delay_read = MAX_DELAY_RD=$(MAX_RD_DELAY)
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min_delay_write = MIN_DELAY_WR=$(MIN_WR_DELAY)
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max_delay_write = MAX_DELAY_WR=$(MAX_WR_DELAY)
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delay_seed = DELAY_SEED=$(DELAY_SEED)
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#(to-do)
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#ddr_init_file = DDR_INIT_FILE=$(DDR_FILE)
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#ddr_start_loc = DDR_FILE_STARTING_LOCATION=$(DDR_FILE_STARTING_LOCATION)
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#ddr_num_bytes = DDR_FILE_NUM_BYTES=$(DDR_FILE_NUM_BYTES)
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CFLAGS = -g0 -O3 -std=c++14 -march=native -D$(ddr_size_def) -D$(page_size_def) -D$(max_inflight_read_requests) -D$(max_inflight_write_requests)\
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-D$(mix_delay_read) -D$(max_delay_read) -D$(min_delay_write) -D$(max_delay_write) -D$(delay_seed)
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#(to-do)-D$(ddr_init_file) -D$(ddr_start_loc) -D$(ddr_num_bytes)
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#Verilator
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################################################################################
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VERILATOR_LINT_IGNORE= -Wno-LITENDIAN -Wno-SYMRSVDWORD
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ifeq ($(TRACE_ENABLE), True)
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VERILATOR_CFLAGS = --trace-fst --trace-structs --CFLAGS "$(CFLAGS) -D TRACE_ON"
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else
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VERILATOR_CFLAGS = --CFLAGS "$(CFLAGS)"
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endif
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VERILATOR_LINT_IGNORE= -Wno-LITENDIAN -Wno-SYMRSVDWORD
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#(to-do)
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#ifeq ($(LOAD_DDR_FROM_FILE), True)
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# VERILATOR_CFLAGS := $(VERILATOR_CFLAGS) -D LOAD_DDR_FROM_FILE"
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#endif
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##################################################################################
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#cva5_sim included as linter requires top-level to have no interfaces
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.PHONY: lint
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lint:
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verilator -cc $(CVA5_HW_SRCS) \
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$(VERILATOR_DIR)/cva5_sim.sv \
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$(CVA5_DIR)/test_benches/sim_stats.sv \
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--top-module cva5_sim \
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--lint-only
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.PHONY: lint-full
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lint-full:
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verilator -cc $(CVA5_HW_SRCS) \
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$(VERILATOR_DIR)/cva5_sim.sv \
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$(CVA5_DIR)/test_benches/sim_stats.sv \
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--top-module cva5_sim \
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--lint-only -Wall
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#Build CVA5 Sim
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$(CVA5_SIM): $(CVA5_HW_SRCS) $(CVA5_SIM_SRCS)
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mkdir -p $(CVA5_SIM_DIR)
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verilator --cc --exe --Mdir $(CVA5_SIM_DIR) -DENABLE_SIMULATION_ASSERTIONS --assert \
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-o cva5-sim \
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$(VERILATOR_LINT_IGNORE) $(VERILATOR_CFLAGS) \
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$(CVA5_SIM_SRCS) \
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$(CVA5_HW_SRCS) $(CVA5_DIR)/test_benches/sim_stats.sv $(CVA5_DIR)/examples/nexys/nexys_config.sv $(CVA5_DIR)/examples/nexys/l1_to_axi.sv $(CVA5_DIR)/examples/nexys/nexys_sim.sv --top-module cva5_sim
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$(MAKE) -C $(CVA5_SIM_DIR) -f Vcva5_sim.mk
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.PHONY: clean-cva5-sim
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clean-cva5-sim:
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rm -rf $(CVA5_SIM_DIR)
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