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4efa1e2d03
* Support for atomic extension A * Support instruction fence extension Zifencei * Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions * Support address translation * Fixes interrupts and exception handling * Adds interrupt controllers * Support coherent multicore systems through a new data cache and arbiter * Multiple bugfixes * Adds new scripts for example systems in Vivado and LiteX * Removes legacy, unused, and broken scripts, examples, and files --------- Co-authored-by: Chris Keilbart <keilbartchris@gmail.com> Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca> Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com> Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca>
78 lines
2.9 KiB
Systemverilog
78 lines
2.9 KiB
Systemverilog
/*
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* Copyright © 2024 Chris Keilbart, Mohammad Shahidzadeh
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Chris Keilbart <ckeilbar@sfu.ca>
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* Mohammad Shahidzadeh <mohammad_shahidzadeh_asadi@sfu.ca>
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*/
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module clint
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#(
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parameter int unsigned NUM_CORES = 1
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) (
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input logic clk,
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input logic rst,
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input logic write_mtime,
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input logic write_mtimecmp,
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input logic write_msip,
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input logic write_upper, //Else lower; mtime and mtimecmp only
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input logic [(NUM_CORES == 1) ? 0 : ($clog2(NUM_CORES)-1) : 0] write_msip_core,
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input logic [(NUM_CORES == 1) ? 0 : ($clog2(NUM_CORES)-1) : 0] write_mtimecmp_core,
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input logic[31:0] write_data,
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output logic[1:0][31:0] mtime,
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output logic[NUM_CORES-1:0][1:0][31:0] mtimecmp,
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output logic[NUM_CORES-1:0] msip,
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output logic[NUM_CORES-1:0] mtip
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);
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////////////////////////////////////////////////////
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//Core Local INTerrupt unit (CLINT)
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//Implements mtime, mtimecmp, mtip, and msip from the RISC-V privileged specification
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//mtime increments at a constant frequency
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//mtip is set when mtime >= mtimecmp
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//mtimecmp and msip are registers
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logic[63:0] mtime_p_1;
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assign mtime_p_1 = {mtime[1], mtime[0]} + 1;
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always_ff @(posedge clk) begin
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if (rst) begin
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mtime <= '0;
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mtimecmp <= '1; //Reset to max to prevent interrupts
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msip <= '0;
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end
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else begin
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for (int i = 0; i < NUM_CORES; i++)
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mtip[i] <= {mtime[1], mtime[0]} >= {mtimecmp[i][1], mtimecmp[i][0]};
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mtime[1] <= write_mtime & write_upper ? write_data : mtime_p_1[63:32];
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mtime[0] <= write_mtime & ~write_upper ? write_data : mtime_p_1[31:0];
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for (int i = 0; i < NUM_CORES; i++) begin
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mtimecmp[i][1] <= write_mtimecmp & write_upper & i == int'(write_mtimecmp_core) ? write_data : mtimecmp[i][1];
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mtimecmp[i][0] <= write_mtimecmp & ~write_upper & i == int'(write_mtimecmp_core) ? write_data : mtimecmp[i][0];
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end
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if (write_msip)
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msip[write_msip_core] <= write_data[0]; //LSB
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end
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end
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endmodule
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