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https://github.com/openhwgroup/cva5.git
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4efa1e2d03
* Support for atomic extension A * Support instruction fence extension Zifencei * Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions * Support address translation * Fixes interrupts and exception handling * Adds interrupt controllers * Support coherent multicore systems through a new data cache and arbiter * Multiple bugfixes * Adds new scripts for example systems in Vivado and LiteX * Removes legacy, unused, and broken scripts, examples, and files --------- Co-authored-by: Chris Keilbart <keilbartchris@gmail.com> Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca> Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com> Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca>
112 lines
3.8 KiB
Systemverilog
112 lines
3.8 KiB
Systemverilog
/*
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* Copyright © 2024 Chris Keilbart
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Chris Keilbart <ckeilbar@sfu.ca>
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*/
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module core_arbiter
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#(
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parameter logic INCLUDE_DCACHE = 1'b1,
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parameter logic INCLUDE_ICACHE = 1'b1,
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parameter logic INCLUDE_MMUS = 1'b1
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) (
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input logic clk,
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input logic rst,
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mem_interface.rw_slave dcache,
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mem_interface.ro_slave icache,
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mem_interface.ro_slave dmmu,
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mem_interface.ro_slave immu,
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mem_interface.mem_master mem
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);
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//Multiplexes memory requests and demultiplexes memory responses
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//If the MMUs are not present the MSB of the memory ID is always 0
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//If the I$ is also not present the entire ID can be set to 0
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logic[3:0] request;
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logic[3:0][31:2] addr;
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logic[3:0][4:0] rlen;
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logic[3:0] rnw;
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logic[3:0] rmw;
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logic[1:0] port;
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////////////////////////////////////////////////////
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//Implementation
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//D$
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assign request[0] = INCLUDE_DCACHE ? dcache.request : 0;
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assign addr[0] = INCLUDE_DCACHE ? dcache.addr : 'x;
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assign rlen[0] = INCLUDE_DCACHE ? dcache.rlen : 'x;
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assign rnw[0] = INCLUDE_DCACHE ? dcache.rnw : 'x;
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assign rmw[0] = INCLUDE_DCACHE ? dcache.rmw : 'x;
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assign mem.wbe = dcache.wbe;
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assign mem.wdata = dcache.wdata;
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assign dcache.inv = mem.inv;
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assign dcache.inv_addr = mem.inv_addr;
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assign dcache.write_outstanding = mem.write_outstanding;
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assign dcache.ack = mem.ack & port == 2'b00;
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assign dcache.rvalid = mem.rvalid & mem.rid == 2'b00;
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assign dcache.rdata = mem.rdata;
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//I$
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assign request[1] = INCLUDE_ICACHE ? icache.request : 0;
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assign addr[1] = INCLUDE_ICACHE ? icache.addr : 'x;
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assign rlen[1] = INCLUDE_ICACHE ? icache.rlen : 'x;
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assign rnw[1] = INCLUDE_ICACHE ? 1 : 'x;
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assign rmw[1] = INCLUDE_ICACHE ? 0 : 'x;
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assign icache.ack = mem.ack & port == 2'b01;
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assign icache.rvalid = mem.rvalid & mem.rid == 2'b01;
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assign icache.rdata = mem.rdata;
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//DMMU
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assign request[2] = INCLUDE_MMUS ? dmmu.request : 0;
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assign addr[2] = INCLUDE_MMUS ? dmmu.addr : 'x;
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assign rlen[2] = INCLUDE_MMUS ? dmmu.rlen : 'x;
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assign rnw[2] = INCLUDE_MMUS ? 1 : 'x;
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assign rmw[2] = INCLUDE_MMUS ? 0 : 'x;
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assign dmmu.rdata = mem.rdata;
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assign dmmu.ack = mem.ack & port == 2'b10;
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assign dmmu.rvalid = mem.rvalid & mem.rid == 2'b10;
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//IMMU
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assign request[3] = INCLUDE_MMUS ? immu.request : 0;
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assign addr[3] = INCLUDE_MMUS ? immu.addr : 'x;
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assign rlen[3] = INCLUDE_MMUS ? immu.rlen : 'x;
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assign rnw[3] = INCLUDE_MMUS ? 1 : 'x;
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assign rmw[3] = INCLUDE_MMUS ? 0 : 'x;
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assign immu.rdata = mem.rdata;
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assign immu.ack = mem.ack & port == 2'b11;
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assign immu.rvalid = mem.rvalid & mem.rid == 2'b11;
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////////////////////////////////////////////////////
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//Arbitration
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round_robin #(.NUM_PORTS(4)) rr (
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.requests(request),
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.grant(mem.request & mem.ack),
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.grantee(port),
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.*);
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assign mem.request = |request;
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assign mem.addr = addr[port];
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assign mem.rlen = rlen[port];
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assign mem.rnw = rnw[port];
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assign mem.rmw = rmw[port];
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assign mem.id = port;
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endmodule
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