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45 lines
1.4 KiB
Systemverilog
45 lines
1.4 KiB
Systemverilog
/*
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* Copyright © 2023 Chris Keilbart, Lesley Shannon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Chris Keilbart <ckeilbar@sfu.ca>
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*/
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module fp_writeback
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import cva5_types::*;
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(
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//Unit writeback
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unit_writeback_interface.wb unit_wb[2],
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//WB output
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output fp_wb_packet_t wb_packet[2]
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);
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//Because there are two writeback ports for the FP register file, no arbitration is needed
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assign wb_packet[0].id = unit_wb[0].id;
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assign wb_packet[0].valid = unit_wb[0].done;
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assign wb_packet[0].data = unit_wb[0].rd;
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assign unit_wb[0].ack = unit_wb[0].done;
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assign wb_packet[1].id = unit_wb[1].id;
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assign wb_packet[1].valid = unit_wb[1].done;
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assign wb_packet[1].data = unit_wb[1].rd;
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assign unit_wb[1].ack = unit_wb[1].done;
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endmodule
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