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cva5/core/memory_sub_units
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mohammadshahidzade 4efa1e2d03
Os fixes6 (#29) 
* Support for atomic extension A
* Support instruction fence extension Zifencei
* Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions
* Support address translation
* Fixes interrupts and exception handling
* Adds interrupt controllers
* Support coherent multicore systems through a new data cache and arbiter
* Multiple bugfixes
* Adds new scripts for example systems in Vivado and LiteX
* Removes legacy, unused, and broken scripts, examples, and files

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Co-authored-by: Chris Keilbart <keilbartchris@gmail.com>
Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca>
Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com>
Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca>
2025-03-11 16:06:16 -07:00
..
avalon_master.sv Os fixes6 (#29) 2025-03-11 16:06:16 -07:00
axi_master.sv Os fixes6 (#29) 2025-03-11 16:06:16 -07:00
local_mem_sub_unit.sv Os fixes6 (#29) 2025-03-11 16:06:16 -07:00
wishbone_master.sv Os fixes6 (#29) 2025-03-11 16:06:16 -07:00