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https://github.com/openhwgroup/cva5.git
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4efa1e2d03
* Support for atomic extension A * Support instruction fence extension Zifencei * Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions * Support address translation * Fixes interrupts and exception handling * Adds interrupt controllers * Support coherent multicore systems through a new data cache and arbiter * Multiple bugfixes * Adds new scripts for example systems in Vivado and LiteX * Removes legacy, unused, and broken scripts, examples, and files --------- Co-authored-by: Chris Keilbart <keilbartchris@gmail.com> Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca> Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com> Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca>
165 lines
No EOL
4.4 KiB
C++
165 lines
No EOL
4.4 KiB
C++
/*
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* Copyright © 2024 Chris Keilbart
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Chris Keilbart <ckeilbar@sfu.ca>
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*/
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#ifndef AXIDDR_H
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#define AXIDDR_H
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#include <queue>
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#include <unordered_map>
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#include <random>
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#include <cstdint>
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#include "Vcva5_sim.h"
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using namespace std;
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//Default defines; can be overridden by command line
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#ifndef NUM_CORES
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#define NUM_CORES 1
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#endif
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#ifndef STARTING_ADDR
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#define STARTING_ADDR 0x80000000
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#endif
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#ifndef PROGRAM_SPACING
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#define PROGRAM_SPACING 0x04000000
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#endif
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//If DETERMINISTIC is set, randomness effecting memory performance is disabled
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#if defined(DETERMINISTIC) && DETERMINISTIC != 0
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#define RVALID_DISTRIBUTION_P 0.0
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#define BVALID_DISTRIBUTION_P 0.0
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#define ARREADY_P 0.0
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#define AWREADY_P 0.0
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#define WREADY_P 0.0
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#define RVALID_P 0.0
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#else
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#define RVALID_DISTRIBUTION_P 0.5
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#define BVALID_DISTRIBUTION_P 0.5
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#define ARREADY_P 0.25
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#define AWREADY_P 0.25
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#define WREADY_P 0.1
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#define RVALID_P 0.1
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#endif
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//Shared RNG and simulation properties
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#define RNG_SEED 101099
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#define RVALID_MIN_LATENCY 20
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#define BVALID_MIN_LATENCY 25
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#define MAX_READS 8
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#define MAX_WRITES 8
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//Certain logic depends on the width of the data bus
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#define MEM_TYPE decltype(*Vcva5_sim::ddr_axi_rdata)
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#define MEM_WORDS (8*sizeof(Vcva5_sim::ddr_axi_rdata)/32)
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#define ADDR_SHIFT_AMT (log2(MEM_WORDS)+2)
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struct request {
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uint32_t address;
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unsigned id;
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unsigned burst;
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unsigned size;
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unsigned length;
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unsigned remaining;
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bool valid;
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};
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struct wdata_entry {
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uint32_t data[MEM_WORDS];
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uint64_t strb; //This caps the bus size to 512
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};
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class AXIMem {
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public:
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//Initialize DDR
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AXIMem(ifstream (&memFiles)[NUM_CORES], Vcva5_sim* tb);
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//Free the memory map
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~AXIMem();
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//Set outputs
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void pre();
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//Respond to inputs
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void post();
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private:
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//Basic initialization that doesn't construct the memory itself
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AXIMem(Vcva5_sim* tb);
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inline void pre_ar();
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inline void pre_aw();
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inline void pre_r();
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inline void pre_w();
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inline void pre_b();
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inline void post_ar();
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inline void post_aw();
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inline void post_r();
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inline void post_w();
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inline void post_b();
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void rst();
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inline void rst_ar();
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inline void rst_aw();
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inline void rst_r();
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inline void rst_w();
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inline void rst_b();
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unsigned log2(unsigned x);
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//Simulation tuneables
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//Latencies follow a shifted geometric distribution
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const unsigned seed = RNG_SEED;
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const unsigned rvalid_min_latency = RVALID_MIN_LATENCY;
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const unsigned bvalid_min_latency = BVALID_MIN_LATENCY;
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const double rvalid_distribution_p = RVALID_DISTRIBUTION_P;
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const double bvalid_distribution_p = BVALID_DISTRIBUTION_P;
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//Bus availability
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static const unsigned max_read_requests = MAX_READS;
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static const unsigned max_write_requests = MAX_WRITES;
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//Odds that it won't be available on any given cycle
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const double arready_p = ARREADY_P;
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const double awready_p = AWREADY_P;
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const double wready_p = WREADY_P;
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const double rvalid_p = RVALID_P;
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//Latency Randomizers
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default_random_engine generator;
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geometric_distribution<unsigned> rvalid_geo;
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geometric_distribution<unsigned> bvalid_geo;
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bernoulli_distribution arready_bern;
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bernoulli_distribution awready_bern;
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bernoulli_distribution wready_bern;
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bernoulli_distribution rvalid_bern;
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//Pointers to Data
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Vcva5_sim *tb;
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uint32_t* wdata_pointer;
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uint32_t* rdata_pointer;
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unordered_map<uint32_t,uint32_t*> mem; //TODO: use the gross fixed array length syntax
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request inflight_r[max_read_requests];
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request inflight_w[max_write_requests];
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queue<wdata_entry> inflight_wdata[max_write_requests];
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queue<unsigned> w_queue;
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queue<unsigned> b_queue;
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queue<unsigned> r_queue;
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unsigned read_burst_count;
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};
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#endif |