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4efa1e2d03
* Support for atomic extension A * Support instruction fence extension Zifencei * Update CSRs to Version 20240411 and include compliant support for Zihpm, Sstc, and Smstateen extensions * Support address translation * Fixes interrupts and exception handling * Adds interrupt controllers * Support coherent multicore systems through a new data cache and arbiter * Multiple bugfixes * Adds new scripts for example systems in Vivado and LiteX * Removes legacy, unused, and broken scripts, examples, and files --------- Co-authored-by: Chris Keilbart <keilbartchris@gmail.com> Co-authored-by: msa417 <msa417@ensc-rcl-14.engineering.sfu.ca> Co-authored-by: Rajnesh Joshi <rajnesh.joshi28@gmail.com> Co-authored-by: Rajnesh Joshi <rajneshj@sfu.ca>
54 lines
1.5 KiB
C++
Executable file
54 lines
1.5 KiB
C++
Executable file
/*
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* Copyright © 2019 Eric Matthews, Chris Keilbart, Lesley Shannon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* Initial code developed under the supervision of Dr. Lesley Shannon,
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* Reconfigurable Computing Lab, Simon Fraser University.
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*
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* Author(s):
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* Eric Matthews <ematthew@sfu.ca>
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* Chris Keilbart <ckeilbar@sfu.ca>
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*/
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#ifndef SIMMEM_H
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#define SIMMEM_H
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#include <fstream>
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#include <unordered_map>
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#include <queue>
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#include <cstdint>
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using namespace std;
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//Default defines; can be overridden by command line
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#ifndef NUM_CORES
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#define NUM_CORES 1
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#endif
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#ifndef STARTING_ADDR
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#define STARTING_ADDR 0x80000000
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#endif
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#ifndef PROGRAM_SPACING
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#define PROGRAM_SPACING 0x04000000
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#endif
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class SimMem {
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public:
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SimMem(ifstream (&memFiles)[NUM_CORES]);
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void write(uint32_t addr, uint32_t data, uint32_t be);
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uint32_t read(uint32_t addr);
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private:
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queue<uint32_t> i_queue[NUM_CORES];
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queue<uint32_t> d_queue[NUM_CORES];
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unordered_map<uint32_t,uint32_t> memory;
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};
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#endif
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