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24 lines
740 B
Verilog
24 lines
740 B
Verilog
//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2019.2.1 (lin64) Build 2729669 Thu Dec 5 04:48:12 MST 2019
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//Date : Fri Jul 24 11:12:29 2020
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//Host : BefuddledZipper-Desktop.hitronhub.home running 64-bit unknown
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//Command : generate_target design_1_wrapper.bd
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//Design : design_1_wrapper
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module design_1_wrapper
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(sin,
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sout);
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input sin;
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output sout;
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wire sin;
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wire sout;
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design_1 design_1_i
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(.sin(sin),
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.sout(sout));
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endmodule
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