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Zavier Aguila 68a7d24aa9 Update README.md
2020-11-11 18:55:57 +00:00
..
scripts Added TCL script to automate setup of example zedboard system. 2020-07-27 15:41:15 -07:00
arm.tcl Edited file header and error msg for DIV, MUL, and ALU 2018-06-05 12:54:42 -07:00
dhrystone.riscv.hw_init Updated binaries. 2019-09-08 14:07:32 -07:00
dhrystone.riscv.sim_init Updated binaries. 2019-09-08 14:07:32 -07:00
README.md Update README.md 2020-11-11 18:55:57 +00:00
simulator_output_example.png Edited file header and error msg for DIV, MUL, and ALU 2018-06-05 12:54:42 -07:00
system.png Edited file header and error msg for DIV, MUL, and ALU 2018-06-05 12:54:42 -07:00
system_periperhals.tcl Edited file header and error msg for DIV, MUL, and ALU 2018-06-05 12:54:42 -07:00
taiga.png Edited file header and error msg for DIV, MUL, and ALU 2018-06-05 12:54:42 -07:00
taiga_small.png Edited file header and error msg for DIV, MUL, and ALU 2018-06-05 12:54:42 -07:00
taiga_wrapper.sv updated wrapper 2019-07-04 10:55:05 -07:00
xilinx_wiring_sample.png Added sample wiring photo. 2019-09-09 13:48:43 -07:00
zedboard.xdc changed constraints. 2019-09-09 13:38:29 -07:00

README.md

Creating a Hardware Project for the Zedboard

We have provided a TCL script that automates the creation of a Taiga system on a zedBoard through Vivado. We also provide the manual steps that the script automate.

Hardware setup scripts and steps found here: Hardware Setup

Simulation setup scripts and steps found here: Simulation Setup