github-mirrors/cva5
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva5.git synced 2025-04-21 04:27:20 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
1 commit 2 branches 1 tag 11 MiB
Find a file
Exact
Eric Matthews 56c889adb9 Initial commit
2017-08-31 19:28:31 -07:00
core Initial commit 2017-08-31 19:28:31 -07:00
l2_arbiter Initial commit 2017-08-31 19:28:31 -07:00
README.md Initial commit 2017-08-31 19:28:31 -07:00

README.md

Taiga

Taiga is a 32-bit RISC-V processor designed for FPGAs supporting the Multiply/Divide and Atomic extensions (RV32IMA). The processor is written in SystemVerilog and has been designed to be both highly extensible and highly configurable.

Taiga is licensed under the Mozilla Public License, v. 2.0 (http://mozilla.org/MPL/2.0/.)