github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-22 21:27:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Update spike for cus_exc:

Browse source 
*Patching the double put_csr in mcause

Signed-off-by: Jules Fauchon <jules.fauchon@thalesgroup.com>
This commit is contained in:
Jules Fauchon 2023-07-11 09:24:46 +02:00
parent 05f95f1a72
commit 009c0348e2
2 changed files with 25 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
cva6/tests/custom/cv_xif/cvxif_macros.h
View file

@ -16,6 +16,6 @@
#define CUS_ISS_EXC(rs1,rs2,rs3,rd) .word 0b##1100000##00000####00000##010##00000##1111011
#define CUS_ADD_RS3(rs1,rs2,rs3,rd) .word 0b##rs3##01##rs2####rs1##000##rd##1111011
#define CUS_ADD_MULTI(rs1,rs2,rs3,rd) .word 0b##0001000##rs2####rs1##000##rd##1111011
#define CUS_EXC(rs1,rs2,rs3,rd) .word 0b####1100000##rs2####rs1##010##00000##1111011
#define CUS_EXC(rs1,rs2,rs3,rd) .word 0b####1100000##rs2####rs1##010##rd##1111011
#define CUS_M_ADD(rs1,rs2,rs3,rd) .word 0b####0000010##rs2####rs1##011##rd##1111011
#define CUS_S_ADD(rs1,rs2,rs3,rd) .word 0b####0000110##rs2####rs1##001##rd##1111011

25
vendor/riscv/riscv-isa-sim/customext/cvxif.cc vendored
View file

@ -142,7 +142,6 @@ class cvxif_t : public cvxif_extn_t
if (r_insn.rs2 != 0 || r_insn.rd != 0){
illegal_instruction();
} else {
p -> put_csr(CSR_MCAUSE, r_insn.rs1);
raise_exception(insn, (reg_t) (r_insn.rs1));
}
break;
@ -161,6 +160,12 @@ class cvxif_t : public cvxif_extn_t
void raise_exception(insn_t insn, reg_t exc_index)
{
switch (exc_index) {
case CAUSE_MISALIGNED_FETCH:
throw trap_instruction_address_misaligned((p ? p->get_state()->v : false), 1, 0, 0);
case CAUSE_FETCH_ACCESS:
throw trap_instruction_access_fault((p ? p->get_state()->v : false), 1, 0, 0);
case CAUSE_BREAKPOINT:
throw trap_breakpoint((p ? p->get_state()->v : false), 1);
case CAUSE_MISALIGNED_LOAD:
// Use 0x1 as perfectly unaligned address;-)
throw trap_load_address_misaligned((p ? p->get_state()->v : false), 1, 0, 0);
@ -173,12 +178,30 @@ class cvxif_t : public cvxif_extn_t
case CAUSE_STORE_ACCESS:
// Use 0x1 as invalid address.
throw trap_store_access_fault((p ? p->get_state()->v : false), 1, 0, 0);
case CAUSE_USER_ECALL:
throw trap_user_ecall();
case CAUSE_SUPERVISOR_ECALL:
throw trap_supervisor_ecall();
case CAUSE_VIRTUAL_SUPERVISOR_ECALL:
throw trap_virtual_supervisor_ecall();
case CAUSE_MACHINE_ECALL:
throw trap_machine_ecall();
case CAUSE_FETCH_PAGE_FAULT:
throw trap_instruction_page_fault((p ? p->get_state()->v : false), 1, 0, 0);
case CAUSE_LOAD_PAGE_FAULT:
// Use 0x1 as always-faulting address.
throw trap_load_page_fault((p ? p->get_state()->v : false), 1, 0, 0);
case CAUSE_STORE_PAGE_FAULT:
// Use 0x1 as always-faulting address.
throw trap_store_page_fault((p ? p->get_state()->v : false), 1, 0, 0);
case CAUSE_FETCH_GUEST_PAGE_FAULT:
throw trap_instruction_guest_page_fault(1, 0, 0);
case CAUSE_LOAD_GUEST_PAGE_FAULT:
throw trap_load_guest_page_fault( 1, 0, 0);
case CAUSE_VIRTUAL_INSTRUCTION:
throw trap_virtual_instruction(1);
case CAUSE_STORE_GUEST_PAGE_FAULT:
throw trap_store_guest_page_fault(1, 0, 0);
default:
illegal_instruction();
}