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🐛 Fix misaligned data in store buffer
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Florian Zaruba
parent
1ec3253441
commit
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5 changed files with 82 additions and 26 deletions
40
README.md
40
README.md
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@ -41,23 +41,23 @@ Check out the [contribution guide](CONTRIBUTING.md)
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# Test Overview
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| **Test Name** | **P/F/U** | **Test Name** | **P/F/U** | **Test Name** | **P/F/U** |
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|---------------|----------------------|---------------|----------------------|---------------|--------------------|
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| add | :white_check_mark: | lb | :white_check_mark: | sll | :white_check_mark: |
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| addi | :white_check_mark: | lbu | :white_check_mark: | slli | :white_check_mark: |
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| addiw | :white_check_mark: | ld | :white_check_mark: | slliw | :white_check_mark: |
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| addw | :white_check_mark: | lh | :white_check_mark: | sllw | :white_check_mark: |
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| and | :white_check_mark: | lhu | :white_check_mark: | slt | :white_check_mark: |
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| andi | :white_check_mark: | lui | :white_check_mark: | slti | :white_check_mark: |
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| auipc | :white_check_mark: | lw | :white_check_mark: | sltiu | :white_check_mark: |
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| beq | :white_check_mark: | lwu | :white_check_mark: | sltu | :white_check_mark: |
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| bge | :white_check_mark: | or | :white_check_mark: | sra | :white_check_mark: |
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| bgeu | :white_check_mark: | ori | :white_check_mark: | srai | :white_check_mark: |
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| blt | :white_check_mark: | sb | :white_large_square: | sraiw | :white_check_mark: |
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| bltu | :white_check_mark: | sd | :white_large_square: | sraw | :white_check_mark: |
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| bne | :white_check_mark: | sh | :white_large_square: | srl | :white_check_mark: |
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| sub | :white_check_mark: | simple | :white_check_mark: | srli | :white_check_mark: |
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| subw | :white_check_mark: | jal | :white_check_mark: | srliw | :white_check_mark: |
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| sw | :white_large_square: | jalr | :white_check_mark: | srlw | :white_check_mark: |
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| xor | :white_check_mark: | | | | |
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| xori | :white_check_mark: | | | | |
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| **Test Name** | **P/F/U** | **Test Name** | **P/F/U** | **Test Name** | **P/F/U** |
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|---------------|--------------------|---------------|--------------------|---------------|--------------------|
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| add | :white_check_mark: | lb | :white_check_mark: | sll | :white_check_mark: |
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| addi | :white_check_mark: | lbu | :white_check_mark: | slli | :white_check_mark: |
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| addiw | :white_check_mark: | ld | :white_check_mark: | slliw | :white_check_mark: |
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| addw | :white_check_mark: | lh | :white_check_mark: | sllw | :white_check_mark: |
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| and | :white_check_mark: | lhu | :white_check_mark: | slt | :white_check_mark: |
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| andi | :white_check_mark: | lui | :white_check_mark: | slti | :white_check_mark: |
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| auipc | :white_check_mark: | lw | :white_check_mark: | sltiu | :white_check_mark: |
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| beq | :white_check_mark: | lwu | :white_check_mark: | sltu | :white_check_mark: |
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| bge | :white_check_mark: | or | :white_check_mark: | sra | :white_check_mark: |
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| bgeu | :white_check_mark: | ori | :white_check_mark: | srai | :white_check_mark: |
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| blt | :white_check_mark: | sb | :white_check_mark: | sraiw | :white_check_mark: |
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| bltu | :white_check_mark: | sd | :white_check_mark: | sraw | :white_check_mark: |
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| bne | :white_check_mark: | sh | :white_check_mark: | srl | :white_check_mark: |
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| sub | :white_check_mark: | simple | :white_check_mark: | srli | :white_check_mark: |
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| subw | :white_check_mark: | jal | :white_check_mark: | srliw | :white_check_mark: |
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| sw | :white_check_mark: | jalr | :white_check_mark: | srlw | :white_check_mark: |
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| xor | :white_check_mark: | | | | |
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| xori | :white_check_mark: | | | | |
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@ -56,7 +56,7 @@ module load_unit (
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input logic data_rvalid_i,
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input logic [63:0] data_rdata_i
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);
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enum logic [2:0] {IDLE, WAIT_GNT, SEND_TAG, ABORT_TRANSLATION, WAIT_FLUSH} NS, CS;
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enum logic [2:0] {IDLE, WAIT_GNT, SEND_TAG, WAIT_PAGE_OFFSET, ABORT_TRANSLATION, WAIT_FLUSH} NS, CS;
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// in order to decouple the response interface from the request interface we need a
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// a queue which can hold all outstanding memory requests
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typedef struct packed {
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@ -141,6 +141,41 @@ module load_unit (
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end else begin
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// stall and wait for the store-buffer to drain
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ready_o = 1'b0;
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// wait for the store buffer to train and the page offset to not match anymore
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NS = WAIT_PAGE_OFFSET;
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end
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end
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end
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// wait here for the page offset to not match anymore
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WAIT_PAGE_OFFSET: begin
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// we are definitely not ready to accept a new request
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// we need unique access to the LSU
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ready_o = 1'b0;
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translation_req_o = 1'b1;
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// we make a new request as soon as the page offset does not match anymore
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// essentially the same part as above
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if (!page_offset_matches_i) begin
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// make a load request to memory
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data_req_o = 1'b1;
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// the translation request we got is valid
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if (translation_valid_i) begin
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// save the physical address for the next cycle
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paddr_n = paddr_i;
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// we got no data grant so wait for the grant before sending the tag
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if (!data_gnt_i) begin
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NS = WAIT_GNT;
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end else begin
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// put the request in the queue
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push = 1'b1;
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// we got a grant so we can send the tag in the next cycle
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NS = SEND_TAG;
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end
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// we got a TLB miss
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end else begin
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// we need to abort the translation and let the PTW walker fix the TLB miss
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NS = ABORT_TRANSLATION;
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ready_o = 1'b0;
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end
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end
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end
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@ -262,9 +297,11 @@ module load_unit (
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// do not push this request
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push = 1'b0;
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end
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// if we just flushed and the queue is not empty or we are getting an rvalid this cycle wait in an extra stage
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// if we just flushed and the queue is not empty or we are getting an rvalid this cycle wait in a extra stage
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if (flush_i && (!empty || data_rvalid_i)) begin
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NS = WAIT_FLUSH;
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end else if (flush_i) begin
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NS = IDLE;
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end
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end
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@ -128,7 +128,7 @@ module scoreboard #(
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mem_n[trans_id_i[i]].sbe.result = wdata_i[i];
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// write the exception back if it is valid
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if (ex_i[i].valid)
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mem_n[trans_id_i[i]].sbe.ex = ex_i[i];
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mem_n[trans_id_i[i]].sbe.ex = ex_i[i];
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end
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end
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@ -59,8 +59,9 @@ module store_unit (
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);
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assign result_o = 64'b0;
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logic [63:0] st_buffer_paddr; // physical address for store
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logic [63:0] st_buffer_data; // store buffer data out
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logic [63:0] st_buffer_paddr; // physical address for store
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logic [63:0] st_buffer_data; // store buffer data out
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logic [63:0] st_data; // aligned data to store buffer
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logic [7:0] st_buffer_be;
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logic st_buffer_valid;
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// store buffer control signals
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@ -108,13 +109,30 @@ module store_unit (
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end
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end
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end
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// -----------
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// Re-aligner
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// -----------
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// re-align the write data to comply with the address offset
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always_comb begin
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st_data = data_i;
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case (vaddr_i[2:0])
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3'b000: st_data = data_i;
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3'b001: st_data = {data_i[55:0], data_i[63:56]};
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3'b010: st_data = {data_i[47:0], data_i[63:48]};
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3'b011: st_data = {data_i[39:0], data_i[63:40]};
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3'b100: st_data = {data_i[31:0], data_i[63:32]};
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3'b101: st_data = {data_i[23:0], data_i[63:24]};
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3'b110: st_data = {data_i[15:0], data_i[63:16]};
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3'b111: st_data = {data_i[7:0], data_i[63:8]};
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endcase
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end
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// ---------------
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// Store Queue
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// ---------------
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store_queue store_queue_i (
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// store queue write port
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.valid_i ( st_valid ),
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.data_i ( st_data ),
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// store buffer in
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.paddr_o ( st_buffer_paddr ),
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.data_o ( st_buffer_data ),
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@ -12,6 +12,7 @@ add wave -noupdate -group ex_stage -group lsu /core_tb/dut/ex_stage_i/lsu_i/*
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add wave -noupdate -group ex_stage -group lsu -group mem_arbiter /core_tb/dut/ex_stage_i/lsu_i/dcache_arbiter_i/*
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add wave -noupdate -group ex_stage -group lsu -group mem_arbiter -group arbiter_fifo /core_tb/dut/ex_stage_i/lsu_i/dcache_arbiter_i/fifo_i/*
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add wave -noupdate -group ex_stage -group lsu -group store_unit /core_tb/dut/ex_stage_i/lsu_i/store_unit_i/*
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add wave -noupdate -group ex_stage -group lsu -group store_unit -group store_queue /core_tb/dut/ex_stage_i/lsu_i/store_unit_i/store_queue_i/*
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add wave -noupdate -group ex_stage -group lsu -group load_unit /core_tb/dut/ex_stage_i/lsu_i/load_unit_i/*
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add wave -noupdate -group ex_stage -group lsu -group load_unit -group fifo /core_tb/dut/ex_stage_i/lsu_i/load_unit_i/fifo_i/*
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add wave -noupdate -group ex_stage -group lsu -group lsu_arbiter /core_tb/dut/ex_stage_i/lsu_i/lsu_arbiter_i/*
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