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Resolved Lint WIDTHTRUNC warnings(1/2) (#1297)

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Fatima Saleem 2023-07-06 14:41:25 +05:00 • committed by GitHub
parent 7068948245
commit 018dbc4210
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11 changed files with 39 additions and 38 deletions
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26
core/cache_subsystem/axi_adapter.sv
View file

@ -170,14 +170,14 @@ module axi_adapter #(
assert (amo_i == ariane_pkg::AMO_NONE)
else $fatal("Bursts of atomic operations are not supported");
axi_req_o.aw.len = BURST_SIZE; // number of bursts to do
axi_req_o.aw.len = BURST_SIZE[7:0]; // number of bursts to do
axi_req_o.w.data = wdata_i[0];
axi_req_o.w.strb = be_i[0];
if (axi_resp_i.w_ready)
cnt_d = BURST_SIZE - 1;
cnt_d = BURST_SIZE[ADDR_INDEX-1:0] - 1;
else
cnt_d = BURST_SIZE;
cnt_d = BURST_SIZE[ADDR_INDEX-1:0];
case ({axi_resp_i.aw_ready, axi_resp_i.w_ready})
2'b11: state_d = WAIT_LAST_W_READY;
@ -198,8 +198,8 @@ module axi_adapter #(
assert (amo_i == ariane_pkg::AMO_NONE)
else $fatal("Bursts of atomic operations are not supported");
axi_req_o.ar.len = BURST_SIZE;
cnt_d = BURST_SIZE;
axi_req_o.ar.len = BURST_SIZE[7:0];
cnt_d = BURST_SIZE[ADDR_INDEX-1:0];
end
if (axi_resp_i.ar_ready) begin
@ -230,12 +230,12 @@ module axi_adapter #(
axi_req_o.w.data = wdata_i[0];
axi_req_o.w.strb = be_i[0];
end else begin
axi_req_o.w.data = wdata_i[BURST_SIZE-cnt_q];
axi_req_o.w.strb = be_i[BURST_SIZE-cnt_q];
axi_req_o.w.data = wdata_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q];
axi_req_o.w.strb = be_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q];
end
axi_req_o.aw_valid = 1'b1;
// we are here because we want to write a cache line
axi_req_o.aw.len = BURST_SIZE;
axi_req_o.aw.len = BURST_SIZE[7:0];
// we got an aw_ready
case ({axi_resp_i.aw_ready, axi_resp_i.w_ready})
// we got an aw ready
@ -266,7 +266,7 @@ module axi_adapter #(
// ~> all data has already been sent, we are only waiting for the aw_ready
WAIT_AW_READY_BURST: begin
axi_req_o.aw_valid = 1'b1;
axi_req_o.aw.len = BURST_SIZE;
axi_req_o.aw.len = BURST_SIZE[7:0];
if (axi_resp_i.aw_ready) begin
state_d = WAIT_B_VALID;
@ -279,8 +279,8 @@ module axi_adapter #(
axi_req_o.w_valid = 1'b1;
if (type_i != ariane_axi::SINGLE_REQ) begin
axi_req_o.w.data = wdata_i[BURST_SIZE-cnt_q];
axi_req_o.w.strb = be_i[BURST_SIZE-cnt_q];
axi_req_o.w.data = wdata_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q];
axi_req_o.w.strb = be_i[BURST_SIZE[ADDR_INDEX-1:0]-cnt_q];
end
// this is the last write
@ -351,9 +351,9 @@ module axi_adapter #(
// ~> cacheline read, single read
WAIT_R_VALID_MULTIPLE, WAIT_R_VALID: begin
if (CRITICAL_WORD_FIRST)
index = addr_offset_q + (BURST_SIZE-cnt_q);
index = addr_offset_q + (BURST_SIZE[ADDR_INDEX-1:0]-cnt_q);
else
index = BURST_SIZE-cnt_q;
index = BURST_SIZE[ADDR_INDEX-1:0]-cnt_q;
// reads are always wrapping here
axi_req_o.r_ready = 1'b1;

7
core/cache_subsystem/wt_dcache_wbuffer.sv
View file

@ -117,7 +117,7 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
logic [riscv::XLEN_ALIGN_BYTES-1:0] bdirty_off;
logic [(riscv::XLEN/8)-1:0] tx_be;
logic [riscv::PLEN-1:0] wr_paddr, rd_paddr;
logic [riscv::PLEN-1:0] wr_paddr, rd_paddr, extract_tag;
logic [DCACHE_TAG_WIDTH-1:0] rd_tag_d, rd_tag_q;
logic [DCACHE_SET_ASSOC-1:0] rd_hit_oh_d, rd_hit_oh_q;
logic check_en_d, check_en_q, check_en_q1;
@ -280,7 +280,8 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
// cache readout & update
///////////////////////////////////////////////////////
assign rd_tag_d = rd_paddr>>DCACHE_INDEX_WIDTH;
assign extract_tag = rd_paddr>>DCACHE_INDEX_WIDTH;
assign rd_tag_d = extract_tag[DCACHE_TAG_WIDTH-1:0];
// trigger TAG readout in cache
assign rd_tag_only_o = 1'b1;
@ -422,7 +423,7 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
// TAG lookup returns, mark corresponding word
if (check_en_q1) begin
if (wbuffer_q[check_ptr_q1].valid) begin
if (|wbuffer_q[check_ptr_q1].valid) begin
wbuffer_d[check_ptr_q1].checked = 1'b1;
wbuffer_d[check_ptr_q1].hit_oh = rd_hit_oh_q;
end

2
core/compressed_decoder.sv
View file

@ -196,7 +196,7 @@ module compressed_decoder #(
// 100: c.subw
// 101: c.addw
illegal_instr_o = 1'b1;
instr_o = {16'b0, instr_i};
instr_o = instr_i;
end
endcase
end

4
core/csr_regfile.sv
View file

@ -441,9 +441,9 @@ module csr_regfile import ariane_pkg::*; #(
// NA4, NAPOT: 1
// TOR, OFF: 0
if (pmpcfg_q[index].addr_mode[1] == 1'b1)
csr_rdata = {10'b0, pmpaddr_q[index][riscv::PLEN-3:0]};
csr_rdata = pmpaddr_q[index][riscv::PLEN-3:0];
else
csr_rdata = {10'b0, pmpaddr_q[index][riscv::PLEN-3:1], 1'b0};
csr_rdata = {pmpaddr_q[index][riscv::PLEN-3:1], 1'b0};
end
default: read_access_exception = 1'b1;
endcase

6
core/cva6.sv
View file

@ -969,9 +969,9 @@ module cva6 import ariane_pkg::*; #(
rvfi_o[i].cause = ex_commit.cause;
rvfi_o[i].mode = debug_mode ? 2'b10 : priv_lvl;
rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1;
rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1;
rvfi_o[i].rs2_addr = commit_instr_id_commit[i].rs2;
rvfi_o[i].rd_addr = commit_instr_id_commit[i].rd;
rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1[4:0];
rvfi_o[i].rs2_addr = commit_instr_id_commit[i].rs2[4:0];
rvfi_o[i].rd_addr = commit_instr_id_commit[i].rd[4:0];
rvfi_o[i].rd_wdata = ariane_pkg::is_rd_fpr(commit_instr_id_commit[i].op) == 0 ? wdata_commit_id[i] : commit_instr_id_commit[i].result;
rvfi_o[i].pc_rdata = commit_instr_id_commit[i].pc;

6
core/decoder.sv
View file

@ -938,7 +938,7 @@ module decoder import ariane_pkg::*; #(
instruction_o.op = ariane_pkg::FCVT_F2F; // fcvt.fmt.fmt - FP to FP Conversion
instruction_o.rs2 = instr.rvftype.rs1; // tie rs2 to rs1 to be safe (vectors use rs2)
imm_select = IIMM; // rs2 holds part of the intruction
if (instr.rftype.rs2[24:23]) illegal_instr = 1'b1; // bits [22:20] used, other bits must be 0
if (|instr.rftype.rs2[24:23]) illegal_instr = 1'b1; // bits [22:20] used, other bits must be 0
// check source format
unique case (instr.rftype.rs2[22:20])
// Only process instruction if corresponding extension is active (static)
@ -964,12 +964,12 @@ module decoder import ariane_pkg::*; #(
5'b11000: begin
instruction_o.op = ariane_pkg::FCVT_F2I; // fcvt.ifmt.fmt - FP to Int Conversion
imm_select = IIMM; // rs2 holds part of the instruction
if (instr.rftype.rs2[24:22]) illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0
if (|instr.rftype.rs2[24:22]) illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0
end
5'b11010: begin
instruction_o.op = ariane_pkg::FCVT_I2F; // fcvt.fmt.ifmt - Int to FP Conversion
imm_select = IIMM; // rs2 holds part of the instruction
if (instr.rftype.rs2[24:22]) illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0
if (|instr.rftype.rs2[24:22]) illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0
end
5'b11100: begin
instruction_o.rs2 = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit

2
core/include/std_cache_pkg.sv
View file

@ -78,7 +78,7 @@ package std_cache_pkg;
function automatic logic [$clog2(ariane_pkg::DCACHE_SET_ASSOC)-1:0] one_hot_to_bin (
input logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] in
);
for (int unsigned i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin
for (logic [$clog2(ariane_pkg::DCACHE_SET_ASSOC)-1:0] i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin
if (in[i])
return i;
end

16
core/re_name.sv
View file

@ -49,22 +49,22 @@ module re_name import ariane_pkg::*; #(
if (issue_ack_i && !flush_unissied_instr_i) begin
// if we acknowledge the instruction tic the corresponding destination register
if (is_rd_fpr(issue_instr_i.op))
re_name_table_fpr_n[issue_instr_i.rd] = re_name_table_fpr_q[issue_instr_i.rd] ^ 1'b1;
re_name_table_fpr_n[issue_instr_i.rd[4:0]] = re_name_table_fpr_q[issue_instr_i.rd[4:0]] ^ 1'b1;
else
re_name_table_gpr_n[issue_instr_i.rd] = re_name_table_gpr_q[issue_instr_i.rd] ^ 1'b1;
re_name_table_gpr_n[issue_instr_i.rd[4:0]] = re_name_table_gpr_q[issue_instr_i.rd[4:0]] ^ 1'b1;
end
// select name bit according to the register file used for source operands
name_bit_rs1 = is_rs1_fpr(issue_instr_i.op) ? re_name_table_fpr_q[issue_instr_i.rs1]
: re_name_table_gpr_q[issue_instr_i.rs1];
name_bit_rs2 = is_rs2_fpr(issue_instr_i.op) ? re_name_table_fpr_q[issue_instr_i.rs2]
: re_name_table_gpr_q[issue_instr_i.rs2];
name_bit_rs1 = is_rs1_fpr(issue_instr_i.op) ? re_name_table_fpr_q[issue_instr_i.rs1[4:0]]
: re_name_table_gpr_q[issue_instr_i.rs1[4:0]];
name_bit_rs2 = is_rs2_fpr(issue_instr_i.op) ? re_name_table_fpr_q[issue_instr_i.rs2[4:0]]
: re_name_table_gpr_q[issue_instr_i.rs2[4:0]];
// rs3 is only used in certain FP operations and held like an immediate
name_bit_rs3 = re_name_table_fpr_q[issue_instr_i.result[4:0]]; // make sure only the addr bits are read
// select name bit according to the state it will have after renaming
name_bit_rd = is_rd_fpr(issue_instr_i.op) ? re_name_table_fpr_q[issue_instr_i.rd] ^ 1'b1
: re_name_table_gpr_q[issue_instr_i.rd] ^ (issue_instr_i.rd != '0); // don't rename x0
name_bit_rd = is_rd_fpr(issue_instr_i.op) ? re_name_table_fpr_q[issue_instr_i.rd[4:0]] ^ 1'b1
: re_name_table_gpr_q[issue_instr_i.rd[4:0]] ^ (issue_instr_i.rd != '0); // don't rename x0
// re-name the source registers
issue_instr_o.rs1 = { ENABLE_RENAME & name_bit_rs1, issue_instr_i.rs1[4:0] };

2
core/scoreboard.sv
View file

@ -191,7 +191,7 @@ module scoreboard #(
// Commit Port
// ------------
// we've got an acknowledge from commit
for (logic [BITS_ENTRIES-1:0] i = 0; i < NR_COMMIT_PORTS; i++) begin
for (logic [NR_COMMIT_PORTS-1:0] i = 0; i < NR_COMMIT_PORTS; i++) begin
if (commit_ack_i[i]) begin
// this instruction is no longer in issue e.g.: it is considered finished
mem_n[commit_pointer_q[i]].issued = 1'b0;

2
core/serdiv.sv
View file

@ -144,7 +144,7 @@ module serdiv import ariane_pkg::*; #(
/////////////////////////////////////
assign cnt_zero = (cnt_q == 0);
assign cnt_d = (load_en) ? div_shift :
assign cnt_d = (load_en) ? div_shift[$clog2(WIDTH)-1:0] :
(~cnt_zero) ? cnt_q - 1 : cnt_q;
always_comb begin : p_fsm

4
core/store_buffer.sv
View file

@ -73,7 +73,7 @@ module store_buffer import ariane_pkg::*; #(
// Speculative Queue - Core Interface
// ----------------------------------------
always_comb begin : core_if
automatic logic [DEPTH_SPEC:0] speculative_status_cnt;
automatic logic [$clog2(DEPTH_SPEC):0] speculative_status_cnt;
speculative_status_cnt = speculative_status_cnt_q;
// we are ready if the speculative and the commit queue have a space left
@ -145,7 +145,7 @@ module store_buffer import ariane_pkg::*; #(
assign mem_paddr_o = commit_queue_n[commit_read_pointer_n].address;
always_comb begin : store_if
automatic logic [DEPTH_COMMIT:0] commit_status_cnt;
automatic logic [$clog2(DEPTH_COMMIT):0] commit_status_cnt;
commit_status_cnt = commit_status_cnt_q;
commit_ready_o = (commit_status_cnt_q < DEPTH_COMMIT);