github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-24 22:27:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 3

riscv-isa-manual: ignore mm-formal.adoc (#2723)
Some checks are pending
bender-up-to-date / bender-up-to-date (push) Waiting to run
Details
ci / build-riscv-tests (push) Waiting to run
Details
ci / execute-riscv64-tests (push) Blocked by required conditions
Details
ci / execute-riscv32-tests (push) Blocked by required conditions
Details

Browse source 
as this appendix requires Java and as it is not relevant for CV32A65X

Signed-off-by: André Sintzoff <andre.sintzoff@thalesgroup.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
This commit is contained in:
André Sintzoff 2025-01-21 17:42:39 +01:00 • committed by GitHub
parent 24c6a891b8
commit 02092dbcf0
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
1 changed files with 7 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

7
docs/riscv-isa/src/mm-formal.adoc Normal file
View file

@ -0,0 +1,7 @@
[appendix]
== Formal Memory Model Specifications, Version 0.1
[[mm-formal]]
ifeval::["{ohg-config}" == "CV32A65X"]
{ohg-config}: No RVWMO memory model.
endif::[]