Update tests' description & enable hvp for coverage report (#1532)

verif/regress/dv-generated-tests.sh

@@ -85,9 +85,8 @@ elif [[ "$list_num" = 6 ]];then
            "riscv_rand_jump_hint_comp_test"
            "riscv_rand_jump_no_cmp_test"
            "riscv_rand_jump_illegal_test"
-           "riscv_arithmetic_basic_sub_prog_test"
            );
-	I=(75 75 50 20);
+	I=(75 75 50);
 fi
 
 if [[ "$list_num" != 0 ]];then
@@ -112,7 +111,7 @@ printf "+=======================================================================
 j=0
 while [[ $j -lt ${#TEST_NAME[@]} ]];do
   cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
-  python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
+  python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imc/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
   n=0
   echo "Generate the test: ${TEST_NAME[j]}"
 #this while loop detects the failed tests from the log file and remove them

verif/sim/Makefile

@@ -253,7 +253,7 @@ vcs-uvm:
           for i in `ls *.$(SIMV_TRACE_EXTN)` ; do mv $$i `dirname $(log)`/`basename $(log) .log`.$(target).$$i ; done || true
 
 generate_cov_dash:
-	urg -dir $(VCS_WORK_DIR)/simv.vdb -format both -group instcov_for_score -tgl portsonly
+	urg -hvp_proj cva6_embedded -format both -group instcov_for_score -hvp_attributes description -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp -tgl portsonly
 
 vcs_clean_all:
 	@echo "[VCS] Cleanup (entire vcs_work dir)"

verif/sim/cva6_base_testlist.yaml

@@ -304,7 +304,6 @@
     +enable_unaligned_load_store=1
     +tvec_alignment=8
     +disable_compressed_instr=1
-    +enable_x_extension=1
   iterations: 2
   gen_test: cva6_instr_base_test_c
   rtl_test: core_base_test
@@ -386,7 +385,7 @@
     Arithmetic instruction test, no load/store/branch instructions
   gen_opts: >
     +instr_cnt=500
-    +num_of_sub_program=5
+    +num_of_sub_program=0
     +directed_instr_0=riscv_int_numeric_corner_stream,4
     +no_fence=1
     +no_data_page=1
@@ -394,32 +393,13 @@
     +no_load_store=1
     +boot_mode=m
     +no_csr_instr=1
-    +illegal_instr_ratio=200
-    +hint_instr_ratio=500
+    +illegal_instr_ratio=100
+    +hint_instr_ratio=100
     +tvec_alignment=8
   iterations: 2
   gen_test: cva6_instr_base_test_c
   rtl_test: core_base_test
 
-- test: riscv_arithmetic_basic_hint_test
-  description: >
-    Arithmetic instruction test, no load/store/branch instructions
-  gen_opts: >
-    +instr_cnt=500
-    +num_of_sub_program=15
-    +directed_instr_0=riscv_int_numeric_corner_stream,4
-    +no_fence=1
-    +no_data_page=1
-    +no_branch_jump=1
-    +boot_mode=m
-    +no_csr_instr=1
-    +enable_interrupt=1
-    +enable_timer_irq=1
-    +hint_instr_ratio=500
-  iterations: 2
-  gen_test: cva6_instr_base_test_c
-  rtl_test: core_base_test
-
 - test: riscv_arithmetic_basic_loop_test
   description: >
     Arithmetic instruction test, no load/store/branch instructions