Merge pull request #2061 from ThalesSiliconSecurity/dev/smoke

Add a short script to challenge generated tests using CVA6-DV

.gitlab-ci/cva6.yml

@@ -208,6 +208,30 @@ pub_smoke:
     - python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log
   artifacts: *artifacts
 
+pub_gen_smoke:
+  stage: smoke tests
+  extends:
+    - .template_job_full_ci
+  parallel:
+    matrix:
+      - DV_SIMULATORS: ["vcs-uvm,spike"]
+  variables:
+    DASHBOARD_JOB_TITLE: "Smoke Generated test $DV_SIMULATORS"
+    DASHBOARD_JOB_DESCRIPTION: "Short generated tests to challenge the CVA6-DV on STEP1 configuration"
+    DASHBOARD_SORT_INDEX: 0
+    DASHBOARD_JOB_CATEGORY: "Basic"
+  before_script:
+    - !reference [.verif_test, before_script]
+  script:
+    # In order to capture logs in case of test failure, the test script cannot fail.
+    - source cva6/regress/smoke-gen_tests.sh || true
+    # The list of files must NOT fail on various DV_SIMULATORS values, so use 'v*_sim' to match
+    # 'veri-testharness_sim', 'vcs-testharness_sim' and 'vcs-uvm_sim' (one of them always applies,
+    # at least until new RTL simulator configurations are added.)
+    - for i in cva6/sim/*/v*_sim/*.log.iss ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
+    - python3 .gitlab-ci/scripts/report_simu.py cva6/sim/logfile.log
+  artifacts: *artifacts
+
 pub_riscv_arch_test:
   extends:
     - .verif_test

cva6/regress/smoke-gen_tests.sh

@@ -0,0 +1,36 @@
+# Copyright 2023 Thales DIS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Ayoub JALALI - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+  echo "Error: RISCV variable undefined"
+  return
+fi
+
+# install the required tools
+source ./cva6/regress/install-cva6.sh
+source ./cva6/regress/install-riscv-dv.sh
+source ./cva6/regress/install-riscv-isa-sim.sh
+
+if ! [ -n "$DV_TARGET" ]; then
+  DV_TARGET=cv32a60x
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+  DV_SIMULATORS=vcs-uvm,spike
+fi
+
+cd cva6/sim/
+cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
+python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
+python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
+python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_unaligned_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300
+make clean_all
+
+cd -

cva6/sim/cva6.py

@@ -379,7 +379,7 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd, linker):
         cmd += (" -march=%s" % isa_ext)
       if not re.search('mabi', cmd):
         cmd += (" -mabi=%s" % mabi)
-      logging.info("Compiling %s" % asm)
+      logging.info("Compiling test : %s" % asm)
       run_cmd_output(cmd.split(), debug_cmd = debug_cmd)
       elf2bin(elf, binary, debug_cmd)