mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-20 04:07:36 -04:00
[RVFI] Change CSR implementation (#1952)
This commit is contained in:
MarioOpenHWGroup
GitHub
parent
5bc063131a
commit
08d098bf51
5 changed files with 164 additions and 300 deletions
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@ -28,10 +28,9 @@ module cva6_rvfi
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output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr_o,
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output rvfi_csr_t rvfi_csr_o
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);
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localparam logic [CVA6Cfg.XLEN-1:0] IsaCode =
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localparam logic [CVA6Cfg.XLEN-1:0] IsaCode =
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(CVA6Cfg.XLEN'(CVA6Cfg.RVA) << 0) // A - Atomic Instructions extension
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| (CVA6Cfg.XLEN'(CVA6Cfg.RVB) << 1) // C - Bitmanip extension
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| (CVA6Cfg.XLEN'(CVA6Cfg.RVC) << 2) // C - Compressed extension
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@ -237,7 +236,7 @@ module cva6_rvfi
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// PACK
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//----------------------------------------------------------------------------------------------------------
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always_comb begin
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always_ff @(posedge clk_i) begin
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for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
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logic exception;
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exception = commit_instr_valid[i][0] && ex_commit_valid;
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@ -275,271 +274,137 @@ module cva6_rvfi
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//----------------------------------------------------------------------------------------------------------
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always_comb begin
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rvfi_csr_o.fflags = CVA6Cfg.FpPresent ?
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'{
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rdata: {{CVA6Cfg.XLEN - 5{1'b0}}, csr.fcsr_q.fflags},
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wdata: {{CVA6Cfg.XLEN - 5{1'b0}}, csr.fcsr_q.fflags},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.frm = CVA6Cfg.FpPresent ?
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'{
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rdata: {{CVA6Cfg.XLEN - 3{1'b0}}, csr.fcsr_q.frm},
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wdata: {{CVA6Cfg.XLEN - 3{1'b0}}, csr.fcsr_q.frm},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.fcsr = CVA6Cfg.FpPresent ?
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'{
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rdata: {{CVA6Cfg.XLEN - 8{1'b0}}, csr.fcsr_q.frm, csr.fcsr_q.fflags},
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wdata: {{CVA6Cfg.XLEN - 8{1'b0}}, csr.fcsr_q.frm, csr.fcsr_q.fflags},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.ftran = CVA6Cfg.FpPresent ?
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'{
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rdata: {{CVA6Cfg.XLEN - 7{1'b0}}, csr.fcsr_q.fprec},
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wdata: {{CVA6Cfg.XLEN - 7{1'b0}}, csr.fcsr_q.fprec},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.dcsr = CVA6Cfg.DebugEn ?
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.dcsr_q},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.dcsr_q},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.dpc = CVA6Cfg.DebugEn ?
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'{rdata: csr.dpc_q, wdata: csr.dpc_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.dscratch0 = CVA6Cfg.DebugEn ?
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'{rdata: csr.dscratch0_q, wdata: csr.dscratch0_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.dscratch1 = CVA6Cfg.DebugEn ?
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'{rdata: csr.dscratch1_q, wdata: csr.dscratch1_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.sstatus = CVA6Cfg.RVS ?
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'{
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rdata: csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0],
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wdata: csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0],
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.sie = CVA6Cfg.RVS ?
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'{rdata: csr.mie_q & csr.mideleg_q, wdata: csr.mie_q & csr.mideleg_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.sip = CVA6Cfg.RVS ?
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'{rdata: csr.mip_q & csr.mideleg_q, wdata: csr.mip_q & csr.mideleg_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.stvec = CVA6Cfg.RVS ?
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'{rdata: csr.stvec_q, wdata: csr.stvec_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.scounteren = CVA6Cfg.RVS ?
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'{rdata: csr.scounteren_q, wdata: csr.scounteren_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.sscratch = CVA6Cfg.RVS ?
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'{rdata: csr.sscratch_q, wdata: csr.sscratch_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.sepc = CVA6Cfg.RVS ?
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'{rdata: csr.sepc_q, wdata: csr.sepc_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.scause = CVA6Cfg.RVS ?
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'{rdata: csr.scause_q, wdata: csr.scause_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.stval = CVA6Cfg.RVS ?
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'{rdata: csr.stval_q, wdata: csr.stval_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.satp = CVA6Cfg.RVS ?
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'{rdata: csr.satp_q, wdata: csr.satp_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.mstatus = '{
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rdata: csr.mstatus_extended,
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wdata: csr.mstatus_extended,
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.mstatush = CVA6Cfg.XLEN == 32 ?
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'{rdata: '0, wdata: '0, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.misa = '{rdata: IsaCode, wdata: IsaCode, rmask: '1, wmask: '1};
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rvfi_csr_o.medeleg = CVA6Cfg.RVS ?
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'{rdata: csr.medeleg_q, wdata: csr.medeleg_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.mideleg = CVA6Cfg.RVS ?
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'{rdata: csr.mideleg_q, wdata: csr.mideleg_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.mie = '{rdata: csr.mie_q, wdata: csr.mie_q, rmask: '1, wmask: '1};
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rvfi_csr_o.mtvec = '{rdata: csr.mtvec_q, wdata: csr.mtvec_q, rmask: '1, wmask: '1};
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rvfi_csr_o.mcounteren = '{
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rdata: csr.mcounteren_q,
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wdata: csr.mcounteren_q,
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.mscratch = '{rdata: csr.mscratch_q, wdata: csr.mscratch_q, rmask: '1, wmask: '1};
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rvfi_csr_o.mepc = '{rdata: csr.mepc_q, wdata: csr.mepc_q, rmask: '1, wmask: '1};
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rvfi_csr_o.mcause = '{rdata: csr.mcause_q, wdata: csr.mcause_q, rmask: '1, wmask: '1};
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rvfi_csr_o.mtval = '{rdata: csr.mtval_q, wdata: csr.mtval_q, rmask: '1, wmask: '1};
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rvfi_csr_o.mip = '{rdata: csr.mip_q, wdata: csr.mip_q, rmask: '1, wmask: '1};
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rvfi_csr_o.menvcfg = '{
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rdata: {{CVA6Cfg.XLEN - 1{1'b0}}, csr.fiom_q},
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wdata: {{CVA6Cfg.XLEN - 1{1'b0}}, csr.fiom_q},
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.menvcfgh = CVA6Cfg.XLEN == 32 ?
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'{rdata: '0, wdata: '0, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.mvendorid = '{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID},
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.marchid = '{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MARCHID},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, ARIANE_MARCHID},
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rmask: '1,
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wmask: '1
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};
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`define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, CSR_SOURCE_NAME) \
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bit [CVA6Cfg.XLEN-1:0] ``CSR_NAME``_d; \
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always_ff @(posedge clk_i) begin \
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``CSR_NAME``_d <= {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}; \
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end \
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always_comb begin \
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rvfi_csr_o.``CSR_NAME = CSR_ENABLE_COND ? \
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'{ rdata: ``CSR_NAME``_d , \
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wdata: { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} }, \
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rmask: '1, wmask: '1} \
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: '0; \
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end
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rvfi_csr_o.mhartid = '{rdata: hart_id_i, wdata: hart_id_i, rmask: '1, wmask: '1};
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rvfi_csr_o.mcountinhibit = '{
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rdata: {{(CVA6Cfg.XLEN - (MHPMCounterNum + 3)) {1'b0}}, csr.mcountinhibit_q},
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wdata: {{(CVA6Cfg.XLEN - (MHPMCounterNum + 3)) {1'b0}}, csr.mcountinhibit_q},
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.mcycle = '{
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rdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
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wdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.mcycleh = CVA6Cfg.XLEN == 32 ?
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.minstret = '{
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rdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
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wdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.minstreth = CVA6Cfg.XLEN == 32 ?
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.cycle = '{
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rdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
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wdata: csr.cycle_q[CVA6Cfg.XLEN-1:0],
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.cycleh = CVA6Cfg.XLEN == 32 ?
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.cycle_q[63:32]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.instret = '{
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rdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
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wdata: csr.instret_q[CVA6Cfg.XLEN-1:0],
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.instreth = CVA6Cfg.XLEN == 32 ?
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.instret_q[63:32]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.dcache = '{rdata: csr.dcache_q, wdata: csr.dcache_q, rmask: '1, wmask: '1};
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rvfi_csr_o.icache = '{rdata: csr.icache_q, wdata: csr.icache_q, rmask: '1, wmask: '1};
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rvfi_csr_o.acc_cons = CVA6Cfg.EnableAccelerator ?
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'{rdata: csr.acc_cons_q, wdata: csr.acc_cons_q, rmask: '1, wmask: '1}
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: '0;
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rvfi_csr_o.pmpcfg0 = '{
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rdata: csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0],
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wdata: csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0],
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.pmpcfg1 = CVA6Cfg.XLEN == 32 ?
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[7:4]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[7:4]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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rvfi_csr_o.pmpcfg2 = '{
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rdata: csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8],
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wdata: csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8],
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rmask: '1,
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wmask: '1
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};
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rvfi_csr_o.pmpcfg3 = CVA6Cfg.XLEN == 32 ?
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'{
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rdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[15:12]},
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wdata: {{CVA6Cfg.XLEN - 32{1'b0}}, csr.pmpcfg_q[15:12]},
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rmask: '1,
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wmask: '1
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}
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: '0;
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`define COMMA ,
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for (int i = 0; i < 16; i++) begin
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rvfi_csr_o.pmpaddr[i] = '{
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rdata:
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csr.pmpcfg_q[i].addr_mode[1]
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== 1'b1 ?
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{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
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: {
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{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}
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,
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csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1]
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,
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1'b0
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},
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wdata:
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csr.pmpcfg_q[i].addr_mode[1]
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== 1'b1 ?
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{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
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: {
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{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}
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,
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csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1]
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,
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1'b0
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},
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rmask: '1,
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wmask: '1
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};
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`define CONNECT_RVFI_SAME(CSR_ENABLE_COND, CSR_NAME) \
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`CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, csr.``CSR_NAME``_q)
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`CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_q.fflags)
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`CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_q.frm)
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`CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, { csr.fcsr_q.frm `COMMA csr.fcsr_q.fflags})
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`CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_q.fprec)
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`CONNECT_RVFI_SAME(CVA6Cfg.FpPresent, dcsr)
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`CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dpc)
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`CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch0)
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`CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch1)
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`CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus,
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csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0])
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`CONNECT_RVFI_FULL(CVA6Cfg.RVS, sie, csr.mie_q & csr.mideleg_q)
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`CONNECT_RVFI_FULL(CVA6Cfg.RVS, sip, csr.mip_q & csr.mideleg_q)
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`CONNECT_RVFI_SAME(CVA6Cfg.RVS, stvec)
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`CONNECT_RVFI_SAME(CVA6Cfg.RVS, scounteren)
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`CONNECT_RVFI_SAME(CVA6Cfg.RVS, sscratch)
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`CONNECT_RVFI_SAME(CVA6Cfg.RVS, sepc)
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`CONNECT_RVFI_SAME(CVA6Cfg.RVS, scause)
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`CONNECT_RVFI_SAME(CVA6Cfg.RVS, stval)
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`CONNECT_RVFI_SAME(CVA6Cfg.RVS, satp)
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`CONNECT_RVFI_FULL(1'b1, mstatus, csr.mstatus_extended)
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`CONNECT_RVFI_FULL(1'b1, mstatush, '0)
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|
||||
`CONNECT_RVFI_FULL(1'b1, misa, IsaCode)
|
||||
|
||||
`CONNECT_RVFI_SAME(CVA6Cfg.RVS, medeleg)
|
||||
`CONNECT_RVFI_SAME(CVA6Cfg.RVS, mideleg)
|
||||
|
||||
`CONNECT_RVFI_SAME(1'b1, mie)
|
||||
`CONNECT_RVFI_SAME(1'b1, mtvec)
|
||||
`CONNECT_RVFI_SAME(1'b1, mcounteren)
|
||||
|
||||
`CONNECT_RVFI_SAME(1'b1, mscratch)
|
||||
|
||||
`CONNECT_RVFI_SAME(1'b1, mepc)
|
||||
`CONNECT_RVFI_SAME(1'b1, mcause)
|
||||
`CONNECT_RVFI_SAME(1'b1, mtval)
|
||||
`CONNECT_RVFI_SAME(1'b1, mip)
|
||||
|
||||
`CONNECT_RVFI_FULL(1'b1, menvcfg, csr.fiom_q)
|
||||
|
||||
`CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, menvcfgh, 0)
|
||||
|
||||
`CONNECT_RVFI_FULL(1'b1, mvendorid, OPENHWGROUP_MVENDORID)
|
||||
`CONNECT_RVFI_FULL(1'b1, marchid, ARIANE_MARCHID)
|
||||
`CONNECT_RVFI_FULL(1'b1, mhartid, hart_id_i)
|
||||
|
||||
`CONNECT_RVFI_SAME(1'b1, mcountinhibit)
|
||||
|
||||
`CONNECT_RVFI_FULL(1'b1, mcycle, csr.cycle_q[CVA6Cfg.XLEN-1:0])
|
||||
`CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, mcycleh, csr.cycle_q[63:32])
|
||||
|
||||
`CONNECT_RVFI_FULL(1'b1, minstret, csr.instret_q[CVA6Cfg.XLEN-1:0])
|
||||
`CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, minstreth, csr.instret_q[63:32])
|
||||
|
||||
`CONNECT_RVFI_FULL(1'b1, cycle, csr.cycle_q[CVA6Cfg.XLEN-1:0])
|
||||
`CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, cycleh, csr.cycle_q[63:32])
|
||||
|
||||
`CONNECT_RVFI_FULL(1'b1, instret, csr.instret_q[CVA6Cfg.XLEN-1:0])
|
||||
`CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, instreth, csr.instret_q[63:32])
|
||||
|
||||
`CONNECT_RVFI_SAME(1'b1, dcache)
|
||||
`CONNECT_RVFI_SAME(1'b1, icache)
|
||||
|
||||
`CONNECT_RVFI_SAME(CVA6Cfg.EnableAccelerator, acc_cons)
|
||||
|
||||
`CONNECT_RVFI_FULL(1'b1, pmpcfg0, csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0])
|
||||
`CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg1, csr.pmpcfg_q[7:4])
|
||||
|
||||
`CONNECT_RVFI_FULL(1'b1, pmpcfg2, csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8])
|
||||
`CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg3, csr.pmpcfg_q[15:12])
|
||||
|
||||
bit [CVA6Cfg.XLEN-1:0] pmpaddr_q;
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 16; i++) begin
|
||||
always_ff @(posedge clk_i) begin
|
||||
pmpaddr_q[i] = (csr.pmpcfg_q[i].addr_mode[1] == 1'b1) ?
|
||||
{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
|
||||
: {{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}} , csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1] , 1'b0 };
|
||||
end
|
||||
always_comb begin
|
||||
rvfi_csr_o.pmpaddr[i] = '{
|
||||
rdata: {'0, pmpaddr_q[i]},
|
||||
wdata:
|
||||
csr.pmpcfg_q[i].addr_mode[1]
|
||||
== 1'b1 ?
|
||||
{{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
|
||||
: {
|
||||
{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}
|
||||
,
|
||||
csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1]
|
||||
,
|
||||
1'b0
|
||||
},
|
||||
rmask: '1,
|
||||
wmask: '1
|
||||
};
|
||||
end
|
||||
end
|
||||
;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -722,9 +722,10 @@ module ariane_testharness #(
|
|||
|
||||
`ifdef VERILATOR
|
||||
initial begin
|
||||
int verbosity = 0;
|
||||
string verbosity = 0;
|
||||
if ($value$plusargs("UVM_VERBOSITY=%s",verbosity)) begin
|
||||
uvm_set_verbosity_level(verbosity);
|
||||
uvm_set_verbosity_level(verbosity);
|
||||
`uvm_info("ariane_testharness", $sformatf("Set UVM_VERBOSITY to %s", verbosity), UVM_NONE)
|
||||
end
|
||||
end
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -57,7 +57,6 @@ module spike #(
|
|||
|
||||
// There is a need of delayed rvfi as the 'csr'_q signal does not have the
|
||||
// written value
|
||||
rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0] rvfi_q;
|
||||
st_rvfi s_core, s_reference_model;
|
||||
logic [63:0] pc64;
|
||||
logic [31:0] rtl_instr;
|
||||
|
|
@ -65,40 +64,34 @@ module spike #(
|
|||
string cause;
|
||||
string instr;
|
||||
|
||||
always_ff @(posedge clk_i) begin
|
||||
if (rst_ni) begin
|
||||
rvfi_q <= rvfi_i;
|
||||
end
|
||||
end
|
||||
|
||||
always_ff @(posedge clk_i) begin
|
||||
if (rst_ni) begin
|
||||
|
||||
for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
|
||||
longint unsigned index = 0;
|
||||
|
||||
if (rvfi_q[i].valid || rvfi_q[i].trap) begin
|
||||
s_core.order = rvfi_q[i].order;
|
||||
s_core.insn = rvfi_q[i].insn;
|
||||
s_core.trap = rvfi_q[i].trap;
|
||||
s_core.trap |= (rvfi_q[i].cause << 1);
|
||||
s_core.halt = rvfi_q[i].halt;
|
||||
s_core.intr = rvfi_q[i].intr;
|
||||
s_core.mode = rvfi_q[i].mode;
|
||||
s_core.ixl = rvfi_q[i].ixl;
|
||||
s_core.rs1_addr = rvfi_q[i].rs1_addr;
|
||||
s_core.rs2_addr = rvfi_q[i].rs2_addr;
|
||||
s_core.rs1_rdata = rvfi_q[i].rs1_rdata;
|
||||
s_core.rs2_rdata = rvfi_q[i].rs2_rdata;
|
||||
s_core.rd1_addr = rvfi_q[i].rd_addr;
|
||||
s_core.rd1_wdata = rvfi_q[i].rd_wdata;
|
||||
s_core.pc_rdata = rvfi_q[i].pc_rdata;
|
||||
s_core.pc_wdata = rvfi_q[i].pc_wdata;
|
||||
s_core.mem_addr = rvfi_q[i].mem_addr;
|
||||
s_core.mem_rmask = rvfi_q[i].mem_rmask;
|
||||
s_core.mem_wmask = rvfi_q[i].mem_wmask;
|
||||
s_core.mem_rdata = rvfi_q[i].mem_rdata;
|
||||
s_core.mem_wdata = rvfi_q[i].mem_wdata;
|
||||
if (rvfi_i[i].valid || rvfi_i[i].trap) begin
|
||||
s_core.order = rvfi_i[i].order;
|
||||
s_core.insn = rvfi_i[i].insn;
|
||||
s_core.trap = rvfi_i[i].trap;
|
||||
s_core.trap |= (rvfi_i[i].cause << 1);
|
||||
s_core.halt = rvfi_i[i].halt;
|
||||
s_core.intr = rvfi_i[i].intr;
|
||||
s_core.mode = rvfi_i[i].mode;
|
||||
s_core.ixl = rvfi_i[i].ixl;
|
||||
s_core.rs1_addr = rvfi_i[i].rs1_addr;
|
||||
s_core.rs2_addr = rvfi_i[i].rs2_addr;
|
||||
s_core.rs1_rdata = rvfi_i[i].rs1_rdata;
|
||||
s_core.rs2_rdata = rvfi_i[i].rs2_rdata;
|
||||
s_core.rd1_addr = rvfi_i[i].rd_addr;
|
||||
s_core.rd1_wdata = rvfi_i[i].rd_wdata;
|
||||
s_core.pc_rdata = rvfi_i[i].pc_rdata;
|
||||
s_core.pc_wdata = rvfi_i[i].pc_wdata;
|
||||
s_core.mem_addr = rvfi_i[i].mem_addr;
|
||||
s_core.mem_rmask = rvfi_i[i].mem_rmask;
|
||||
s_core.mem_wmask = rvfi_i[i].mem_wmask;
|
||||
s_core.mem_rdata = rvfi_i[i].mem_rdata;
|
||||
s_core.mem_wdata = rvfi_i[i].mem_wdata;
|
||||
|
||||
`define GET_RVFI_CSR(CSR_ADDR, CSR_NAME, CSR_INDEX) \
|
||||
s_core.csr_valid[CSR_INDEX] = 1; \
|
||||
|
|
|
|||
|
|
@ -1,5 +1,13 @@
|
|||
# CVA6 project root
|
||||
export ROOT_PROJECT=$(readlink -f $(dirname "${BASH_SOURCE[0]}")/../..)
|
||||
if [ -n "$BASH_VERSION" ]; then
|
||||
SCRIPT_PATH="$BASH_SOURCE[0]"
|
||||
elif [ -n "$ZSH_VERSION" ]; then
|
||||
SCRIPT_PATH="${(%):-%N}"
|
||||
else
|
||||
echo "Error: Non recognized shell."
|
||||
return
|
||||
fi
|
||||
export ROOT_PROJECT=$(readlink -f $(dirname "${SCRIPT_PATH}")/../..)
|
||||
|
||||
export RTL_PATH="$ROOT_PROJECT/"
|
||||
export TB_PATH="$ROOT_PROJECT/verif/tb/core"
|
||||
|
|
|
|||
|
|
@ -365,9 +365,6 @@ function void uvmt_cva6_base_test_c::pkg_to_cfg();
|
|||
st_core_cntrl_cfg st = env_cfg.to_struct();
|
||||
st = cva6pkg_to_core_cntrl_cfg(st);
|
||||
|
||||
// TODO Remove when the functionality works
|
||||
st.disable_all_csr_checks = 1;
|
||||
|
||||
env_cfg.from_struct(st);
|
||||
|
||||
env_cfg.post_randomize();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue