Put timer to external (tightly coupled) peripheral

src/ariane.sv

@@ -33,7 +33,6 @@ module ariane
     (
         input  logic                           clk_i,
         input  logic                           rst_ni,
-        input  logic [63:0]                    time_i,
         input  logic                           clock_en_i,    // enable clock, otherwise it is gated
         input  logic                           test_en_i,     // enable all clock gates for testing
 
@@ -72,6 +71,9 @@ module ariane
         output logic                           irq_ack_o,
         input  logic                           irq_sec_i,
         output logic                           sec_lvl_o,
+        // Timer facilities
+        input  logic [63:0]                    time_i,        // global time (most probably coming from an RTC)
+        input  logic                           time_irq_i,    // timer interrupt in
 
         // Debug Interface
         input  logic                           debug_req_i,

src/csr_regfile.sv

@@ -25,6 +25,8 @@ module csr_regfile #(
     input  logic                  clk_i,                      // Clock
     input  logic                  rst_ni,                     // Asynchronous reset active low
     input  logic [63:0]           time_i,                     // Platform Timer
+    input  logic                  time_irq_i,                 // Timer threw an interrupt
+
     // send a flush request out if a CSR with a side effect has changed (e.g. written)
     output logic                  flush_o,
     output logic                  halt_csr_o,                 // halt requested
@@ -313,6 +315,8 @@ module csr_regfile #(
         mip_n[11] = mip_q[11] & irq_i[0];
         // Supervisor Mode External Interrupt Pending
         mip_n[9] = mip_q[9] & irq_i[1];
+        // Timer interrupt pending, coming from platform timer
+        mip_n[7] = time_irq_i;
 
         // -----------------------
         // Manage Exception Stack

tb

@@ -1 +1 @@
-Subproject commit 7c77b5bdd7ddc82a9be4331405eefd0eafad5752
+Subproject commit d6781f3cc6e6144f850c7480103bfd7df524b2b6