load_store_unit: Fix #70 default assignment issue

CHANGELOG.md

@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 - Fix bug in wt_axi_adapter (only appeared when dcache lines were wider than icache lines)
 - Fix potentially long timing path in `axi_lite_interface`
+- Fix VCS elab warning in `load_store_unit`
 
 ### 4.1.2
 

src/load_store_unit.sv

@@ -435,13 +435,13 @@ module lsu_bypass (
         end
 
         if (pop_st_i && pop_ld_i)
-            mem_n = '{default: 0};
+            mem_n = '0;
 
         if (flush_i) begin
             status_cnt = '0;
             write_pointer = '0;
             read_pointer = '0;
-            mem_n = '{default: 0};
+            mem_n = '0;
         end
         // default assignments
         read_pointer_n  = read_pointer;
@@ -461,7 +461,7 @@ module lsu_bypass (
     // registers
     always_ff @(posedge clk_i or negedge rst_ni) begin
         if (~rst_ni) begin
-            mem_q           <= '{default: 0};
+            mem_q           <= '0;
             status_cnt_q    <= '0;
             write_pointer_q <= '0;
             read_pointer_q  <= '0;