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Small fixes and verilator update

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This commit is contained in:
Florian Zaruba 2018-07-24 22:17:12 -07:00
parent f091dbce57
commit 09981eabc0
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GPG key ID: E742FFE8EC38A792
6 changed files with 10 additions and 8 deletions
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2
Makefile
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@ -148,6 +148,8 @@ verilate:
src/debug/debug_rom/debug_rom.sv \
src/util/generic_fifo.sv \
tb/common/SimDTM.sv \
tb/common/SimJTAG.sv \
tb/common/pulp_sync.sv \
bootrom/bootrom.sv \
src/util/cluster_clock_gating.sv \
src/util/behav_sram.sv \

2
ci/install-verilator.sh
View file

@ -5,7 +5,7 @@ cd $ROOT/tmp
if [ ! -e "$ROOT/tmp/bin/verilator" ]; then
echo "Installing Verilator"
wget https://www.veripool.org/ftp/verilator-3.918.tgz
wget https://www.veripool.org/ftp/verilator-3.924.tgz
tar xzf verilator*.t*gz && cd verilator-*
autoconf && ./configure --prefix="$ROOT/tmp" && make -j2 && make test && make install
else

2
ci/run-tests.sh
View file

@ -2,4 +2,4 @@
set -e
ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
# run the tests in parallel, 4 at a time
printf "$(xargs printf '\n%s' < $ROOT/ci/test.list | cut -b 1-)" | xargs -n1 -P4 -I{} $ROOT/build/Variane_testharness tmp/riscv-tests/build/isa/{}
printf "$(xargs printf '\n%s' < ${ROOT}/ci/test.list | cut -b 1-)" | xargs -n1 -P4 -I{} ${ROOT}/build/Variane_testharness tmp/riscv-tests/build/isa/{}

2
src/debug/dmi_cdc.sv
View file

@ -74,7 +74,7 @@ module dmi_cdc (
) i_dmi_cdc_jtag (
.tck_i,
.trst_ni,
.mem_req_i,
.mem_req_i ( mem_valid_i ),
.mem_gnt_o,
.mem_addr_i,
.mem_we_i,

8
src/debug/dmi_jtag.sv
View file

@ -99,13 +99,13 @@ module dmi_jtag (
case (state_q)
Idle: begin
// make sure that no error is sticky
if (dmi_access && update_dr && (dmi_error_q == 0)) begin
if (dmi_access && update_dr && (error_q == 0)) begin
// save address and value
address_d = dmi.address;
data_d = dmi.data;
if (dtm_op_t'(dmi.op) == dm::DTM_READ) begin
if (dm::dtm_op_t'(dmi.op) == dm::DTM_READ) begin
state_d = Read;
end else if (dtm_op_t'(dmi.op) == dm::DTM_WRITE) begin
end else if (dm::dtm_op_t'(dmi.op) == dm::DTM_WRITE) begin
state_d = Write;
end
// else this is a nop and we can stay here
@ -170,7 +170,7 @@ module dmi_jtag (
always_ff @(posedge tck_i or negedge trst_ni) begin
if (~trst_ni) begin
dr_q <= '0;
state_d <= Idle;
state_q <= Idle;
address_q <= '0;
data_q <= '0;
error_q <= '0;

2
tb

@ -1 +1 @@
Subproject commit 70397e11ee3b0243f53a34facd64e9ac5b8a576c
Subproject commit 523f5345a7d3c17479501961bc905fecdfc983b9