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Generate cv32a60x design document (#2924)

Browse source 
Fix cv32a65x design document

Update CVXIF design documentation

Remove DCACHE/ICACHE CSRs from spec, doc, and config files.

Remove cache description from cv32a60x

Update OBI interfaces specification for cv32a60x
This commit is contained in:
JeanRochCoulon 2025-04-15 09:42:16 +02:00 • committed by GitHub
parent e4a8ffb1f6
commit 0999d3480d
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GPG key ID: B5690EEEBB952194
38 changed files with 2758 additions and 298 deletions
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5
docs/scripts/spec_builder.py
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@ -106,7 +106,7 @@ def print_to_rst(pathout, target, module, ports, comments):
fout.write("\n")
if len(comments) != 0:
fout.write(
f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n"
f"Due to {target.upper()} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n"
)
fout.write("\n")
for comment in comments:
@ -138,7 +138,7 @@ def print_to_adoc(pathout, target, module, ports, comments):
if len(comments) != 0:
fout.write(
f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n\n"
f"Due to {target.upper()} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n\n"
)
for comment in comments:
fout.write(f"{comment[0]},::\n* {comment[1]}\n")
@ -189,6 +189,7 @@ def main():
if args.gen_ports_folder is not None:
file = []
file.append("../core/cva6.sv")
file.append("../core/cva6_pipeline.sv")
file.append("../core/frontend/frontend.sv")
file.append("../core/frontend/bht.sv")
file.append("../core/frontend/btb.sv")