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🐛 Fix problem with exception during AMO
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parent
2923e1cb1e
commit
09c1469406
2 changed files with 7 additions and 6 deletions
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@ -33,6 +33,7 @@ module amo_buffer (
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input logic no_st_pending_i // there is currently no store pending anymore
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);
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logic flush_amo_buffer;
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logic amo_valid;
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typedef struct packed {
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ariane_pkg::amo_t op;
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@ -44,7 +45,7 @@ module amo_buffer (
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amo_op_t amo_data_in, amo_data_out;
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// validate this request as soon as all stores have drained and the AMO is in the commit stage
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assign amo_req_o.req = no_st_pending_i & amo_valid_commit_i;
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assign amo_req_o.req = no_st_pending_i & amo_valid_commit_i & amo_valid;
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assign amo_req_o.amo_op = amo_data_out.op;
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assign amo_req_o.size = amo_data_out.size;
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assign amo_req_o.operand_a = amo_data_out.paddr;
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@ -69,7 +70,7 @@ module amo_buffer (
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.rst_ni ( rst_ni ),
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.flush_i ( flush_amo_buffer ),
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.testmode_i ( 1'b0 ),
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.full_o ( ), // not used as this FIFO has only a single element depth
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.full_o ( amo_valid ),
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.empty_o ( ready_o ),
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.alm_full_o ( ), // left open
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.alm_empty_o ( ), // left open
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@ -157,7 +157,7 @@ module commit_stage #(
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// ------------------
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// AMO
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// ------------------
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if (instr_0_is_amo) begin
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if (instr_0_is_amo && !exception_o.valid) begin
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// AMO finished
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commit_ack_o[0] = amo_resp_i.ack;
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// flush the pipeline
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@ -226,15 +226,15 @@ module commit_stage #(
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// ------------------------
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// check for CSR interrupts (e.g.: normal interrupts which get triggered here)
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// by putting interrupts here we give them precedence over any other exception
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if (csr_exception_i.valid && csr_exception_i.cause[63]) begin
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// Don't take the interrupt if we are committing an AMO.
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if (csr_exception_i.valid && csr_exception_i.cause[63] && !amo_valid_commit_o) begin
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exception_o = csr_exception_i;
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exception_o.tval = commit_instr_i[0].ex.tval;
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end
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end
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// Don't take any exceptions iff:
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// - If we halted the processor
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// - We are committing an AMO
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if (halt_i || amo_valid_commit_o) begin
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if (halt_i) begin
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exception_o.valid = 1'b0;
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end
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end
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