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update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 (#2323)

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since last riscv-isa-manual update (CVA6 commit 105d3601b):
- minor documentation changes
- use of docs-resources submodule inside riscv-isa-manual
- requires asciidoctor-lists
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André Sintzoff 2024-07-05 12:06:16 +02:00 • committed by GitHub
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@ -5,7 +5,7 @@
<meta http-equiv="X-UA-Compatible" content="IE=edge"> <meta http-equiv="X-UA-Compatible" content="IE=edge">
<meta name="viewport" content="width=device-width, initial-scale=1.0"> <meta name="viewport" content="width=device-width, initial-scale=1.0">
<meta name="generator" content="Asciidoctor 2.0.22"> <meta name="generator" content="Asciidoctor 2.0.22">
<meta name="description" content="Volume I - Unprivileged Architecture"> <meta name="description" content="Unprivileged Architecture">
<title>The RISC-V Instruction Set Manual for CV32A65X: Volume I - Unprivileged Architecture</title> <title>The RISC-V Instruction Set Manual for CV32A65X: Volume I - Unprivileged Architecture</title>
<link rel="stylesheet" href="https://fonts.googleapis.com/css?family=Open+Sans:300,300italic,400,400italic,600,600italic%7CNoto+Serif:400,400italic,700,700italic%7CDroid+Sans+Mono:400,700"> <link rel="stylesheet" href="https://fonts.googleapis.com/css?family=Open+Sans:300,300italic,400,400italic,600,600italic%7CNoto+Serif:400,400italic,700,700italic%7CDroid+Sans+Mono:400,700">
<style> <style>
@ -440,7 +440,7 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
<div id="header"> <div id="header">
<h1>The RISC-V Instruction Set Manual for CV32A65X: Volume I - Unprivileged Architecture</h1> <h1>The RISC-V Instruction Set Manual for CV32A65X: Volume I - Unprivileged Architecture</h1>
<div class="details"> <div class="details">
<span id="revnumber">version 20240612</span> <span id="revnumber">version 20240703</span>
</div> </div>
<div id="toc" class="toc2"> <div id="toc" class="toc2">
<div id="toctitle">Table of Contents</div> <div id="toctitle">Table of Contents</div>
@ -1019,7 +1019,7 @@ Jean-Roch Coulon, André Sintzoff.</em></p>
OpenHW Group CV32A65X.</p> OpenHW Group CV32A65X.</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p><strong class="big"><em>Preface to Document Version 20240612</em></strong></p> <p><strong class="big"><em>Preface to Document Version 20240703</em></strong></p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>This document describes the RISC-V unprivileged architecture.</p> <p>This document describes the RISC-V unprivileged architecture.</p>
@ -1138,6 +1138,11 @@ to change before ratification.</p>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td> <td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td>
</tr> </tr>
<tr> <tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zabha</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>RVWMO</strong></p></td> <td class="tableblock halign-center valign-top"><p class="tableblock"><strong>RVWMO</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>2.0</strong></p></td> <td class="tableblock halign-left valign-top"><p class="tableblock"><strong>2.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td> <td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
@ -1292,6 +1297,16 @@ to change before ratification.</p>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td> <td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td> <td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr> </tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zicfiss</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zicfilp</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
</tbody> </tbody>
</table> </table>
<div class="paragraph"> <div class="paragraph">
@ -10047,7 +10062,7 @@ Zcb can be implemented on <em>any</em> CPU as the instructions are 16-bit versio
<i class="fa icon-note" title="Note"></i> <i class="fa icon-note" title="Note"></i>
</td> </td>
<td class="content"> <td class="content">
<em>c.sext.w</em> is a pseudo-instruction for <em>c.addiw rd, 0</em> (RV64) <em>c.sext.w</em> is a pseudoinstruction for <em>c.addiw rd, 0</em> (RV64)
</td> </td>
</tr> </tr>
</table> </table>
@ -10503,7 +10518,7 @@ Zcmt is primarily targeted at embedded class CPUs due to implementation complexi
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre> X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre>
</div> </div>
@ -10573,7 +10588,7 @@ X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre> X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div> </div>
@ -10643,7 +10658,7 @@ X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre> X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div> </div>
@ -10713,7 +10728,7 @@ X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre> mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre>
</div> </div>
@ -10783,7 +10798,7 @@ mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c)</code></pre> mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c)</code></pre>
</div> </div>
@ -11572,7 +11587,7 @@ It is implementation defined whether interrupts can also be taken during the seq
<div class="ulist"> <div class="ulist">
<ul> <ul>
<li> <li>
<p>A sequence of stores writing the bytes required by the pseudo-code</p> <p>A sequence of stores writing the bytes required by the pseudocode</p>
<div class="ulist"> <div class="ulist">
<ul> <ul>
<li> <li>
@ -11654,7 +11669,7 @@ addi sp, sp, -64</code></pre>
<div class="ulist"> <div class="ulist">
<ul> <ul>
<li> <li>
<p>A sequence of loads reading the bytes required by the pseudo-code.</p> <p>A sequence of loads reading the bytes required by the pseudocode.</p>
<div class="ulist"> <div class="ulist">
<ul> <ul>
<li> <li>
@ -12040,11 +12055,11 @@ as defined above.</p>
<p>Operation:</p> <p>Operation:</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p> <p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8; if (XLEN==32) bytes=4; else bytes=8;
@ -12062,11 +12077,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p> <p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp-=stack_adj;</code></pre> sp-=stack_adj;</code></pre>
</div> </div>
@ -12266,11 +12281,11 @@ as defined above.</p>
<p>Operation:</p> <p>Operation:</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p> <p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8; if (XLEN==32) bytes=4; else bytes=8;
@ -12288,11 +12303,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p> <p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp+=stack_adj;</code></pre> sp+=stack_adj;</code></pre>
</div> </div>
@ -12487,11 +12502,11 @@ switch (rlist) {
<p>Operation:</p> <p>Operation:</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p> <p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8; if (XLEN==32) bytes=4; else bytes=8;
@ -12509,7 +12524,7 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p> <p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div> </div>
<div class="admonitionblock note"> <div class="admonitionblock note">
<table> <table>
@ -12527,7 +12542,7 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
asm("li a0, 0"); asm("li a0, 0");
sp+=stack_adj; sp+=stack_adj;
@ -12727,11 +12742,11 @@ switch (rlist) {
<p>Operation:</p> <p>Operation:</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p> <p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8; if (XLEN==32) bytes=4; else bytes=8;
@ -12749,11 +12764,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p> <p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp+=stack_adj; sp+=stack_adj;
asm("ret");</code></pre> asm("ret");</code></pre>
@ -12812,7 +12827,7 @@ The execution is atomic, so it is not possible to observe state where only one o
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space. <p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space.
The mapping between them is specified in the pseudo-code below.</p> The mapping between them is specified in the pseudocode below.</p>
</div> </div>
<div class="admonitionblock note"> <div class="admonitionblock note">
<table> <table>
@ -12845,7 +12860,7 @@ The mapping between them is specified in the pseudo-code below.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) { if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) {
reserved(); reserved();
} }
@ -12894,7 +12909,7 @@ The execution is atomic, so it is not possible to observe state where only one o
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space. <p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space.
The mapping between them is specified in the pseudo-code below.</p> The mapping between them is specified in the pseudocode below.</p>
</div> </div>
<div class="admonitionblock note"> <div class="admonitionblock note">
<table> <table>
@ -12927,7 +12942,7 @@ The mapping between them is specified in the pseudo-code below.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) { if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) {
reserved(); reserved();
} }
@ -13208,7 +13223,7 @@ attempt to program different modes and read back the values to see which are ava
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
# target_address is temporary internal state, it doesn't represent a real register # target_address is temporary internal state, it doesn't represent a real register
# InstMemory is byte indexed # InstMemory is byte indexed
@ -13311,7 +13326,7 @@ j target_address[XLEN-1:0]&amp;~0x1;</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
# target_address is temporary internal state, it doesn't represent a real register # target_address is temporary internal state, it doesn't represent a real register
# InstMemory is byte indexed # InstMemory is byte indexed
@ -19545,7 +19560,7 @@ categories: <em>standard</em> versus <em>non-standard</em>.</p>
<li> <li>
<p>A standard extension is one that is generally useful and that is <p>A standard extension is one that is generally useful and that is
designed to not conflict with any other standard extension. Currently, designed to not conflict with any other standard extension. Currently,
"MAFDQLCBTPV", described in other chapters of this manual, are either "MAFDQCBTPV", described in other chapters of this manual, are either
complete or planned standard extensions.</p> complete or planned standard extensions.</p>
</li> </li>
<li> <li>
@ -24636,7 +24651,7 @@ sizes. Misaligned accesses are broken up into single-byte accesses.</p>
semantics (RV64I and A), are integrated into the <code>rmem</code> exploration tool semantics (RV64I and A), are integrated into the <code>rmem</code> exploration tool
(<a href="https://github.com/rems-project/rmem" class="bare">github.com/rems-project/rmem</a>). <code>rmem</code> can explore litmus tests (<a href="https://github.com/rems-project/rmem" class="bare">github.com/rems-project/rmem</a>). <code>rmem</code> can explore litmus tests
(see <a href="#litmustests">Section A.2</a>) and small ELF binaries (see <a href="#litmustests">Section A.2</a>) and small ELF binaries
exhaustively, pseudo-randomly and interactively. In <code>rmem</code>, the ISA exhaustively, pseudorandomly and interactively. In <code>rmem</code>, the ISA
semantics is expressed explicitly in Sail (see semantics is expressed explicitly in Sail (see
<a href="https://github.com/rems-project/sail" class="bare">github.com/rems-project/sail</a> for the Sail language, and <a href="https://github.com/rems-project/sail" class="bare">github.com/rems-project/sail</a> for the Sail language, and
<a href="https://github.com/rems-project/sail-riscv" class="bare">github.com/rems-project/sail-riscv</a> for the RISC-V ISA model), <a href="https://github.com/rems-project/sail-riscv" class="bare">github.com/rems-project/sail-riscv</a> for the RISC-V ISA model),
@ -26330,7 +26345,7 @@ not supported.</p>
</div> </div>
<div id="footer"> <div id="footer">
<div id="footer-text"> <div id="footer-text">
Version 20240612<br> Version 20240703<br>
</div> </div>
</div> </div>
</body> </body>

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@ -4,26 +4,24 @@
<meta charset="UTF-8"> <meta charset="UTF-8">
<meta http-equiv="X-UA-Compatible" content="IE=edge"> <meta http-equiv="X-UA-Compatible" content="IE=edge">
<meta name="viewport" content="width=device-width, initial-scale=1.0"> <meta name="viewport" content="width=device-width, initial-scale=1.0">
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<meta name="description" content="Volume I - Unprivileged Architecture"> <meta name="description" content="Unprivileged Architecture">
<title>The RISC-V Instruction Set Manual for CV64A6_MMU: Volume I - Unprivileged Architecture</title> <title>The RISC-V Instruction Set Manual for CV64A6_MMU: Volume I - Unprivileged Architecture</title>
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<div id="header"> <div id="header">
<h1>The RISC-V Instruction Set Manual for CV64A6_MMU: Volume I - Unprivileged Architecture</h1> <h1>The RISC-V Instruction Set Manual for CV64A6_MMU: Volume I - Unprivileged Architecture</h1>
<div class="details"> <div class="details">
<span id="revnumber">version 20240612</span> <span id="revnumber">version 20240703</span>
</div> </div>
<div id="toc" class="toc2"> <div id="toc" class="toc2">
<div id="toctitle">Table of Contents</div> <div id="toctitle">Table of Contents</div>
@ -1032,7 +1031,7 @@ Jean-Roch Coulon, André Sintzoff.</em></p>
OpenHW Group CV64A6_MMU.</p> OpenHW Group CV64A6_MMU.</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p><strong class="big"><em>Preface to Document Version 20240612</em></strong></p> <p><strong class="big"><em>Preface to Document Version 20240703</em></strong></p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>This document describes the RISC-V unprivileged architecture.</p> <p>This document describes the RISC-V unprivileged architecture.</p>
@ -1151,6 +1150,11 @@ to change before ratification.</p>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td> <td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td>
</tr> </tr>
<tr> <tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zabha</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>RVWMO</strong></p></td> <td class="tableblock halign-center valign-top"><p class="tableblock"><strong>RVWMO</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>2.0</strong></p></td> <td class="tableblock halign-left valign-top"><p class="tableblock"><strong>2.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td> <td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
@ -1305,6 +1309,16 @@ to change before ratification.</p>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td> <td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td> <td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr> </tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zicfiss</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zicfilp</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
</tbody> </tbody>
</table> </table>
<div class="paragraph"> <div class="paragraph">
@ -10398,7 +10412,7 @@ Zcb can be implemented on <em>any</em> CPU as the instructions are 16-bit versio
<i class="fa icon-note" title="Note"></i> <i class="fa icon-note" title="Note"></i>
</td> </td>
<td class="content"> <td class="content">
<em>c.sext.w</em> is a pseudo-instruction for <em>c.addiw rd, 0</em> (RV64) <em>c.sext.w</em> is a pseudoinstruction for <em>c.addiw rd, 0</em> (RV64)
</td> </td>
</tr> </tr>
</table> </table>
@ -10854,7 +10868,7 @@ Zcmt is primarily targeted at embedded class CPUs due to implementation complexi
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre> X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre>
</div> </div>
@ -10924,7 +10938,7 @@ X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre> X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div> </div>
@ -10994,7 +11008,7 @@ X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre> X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div> </div>
@ -11064,7 +11078,7 @@ X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre> mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre>
</div> </div>
@ -11134,7 +11148,7 @@ mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c)</code></pre> mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c)</code></pre>
</div> </div>
@ -11923,7 +11937,7 @@ It is implementation defined whether interrupts can also be taken during the seq
<div class="ulist"> <div class="ulist">
<ul> <ul>
<li> <li>
<p>A sequence of stores writing the bytes required by the pseudo-code</p> <p>A sequence of stores writing the bytes required by the pseudocode</p>
<div class="ulist"> <div class="ulist">
<ul> <ul>
<li> <li>
@ -12005,7 +12019,7 @@ addi sp, sp, -64</code></pre>
<div class="ulist"> <div class="ulist">
<ul> <ul>
<li> <li>
<p>A sequence of loads reading the bytes required by the pseudo-code.</p> <p>A sequence of loads reading the bytes required by the pseudocode.</p>
<div class="ulist"> <div class="ulist">
<ul> <ul>
<li> <li>
@ -12391,11 +12405,11 @@ as defined above.</p>
<p>Operation:</p> <p>Operation:</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p> <p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8; if (XLEN==32) bytes=4; else bytes=8;
@ -12413,11 +12427,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p> <p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp-=stack_adj;</code></pre> sp-=stack_adj;</code></pre>
</div> </div>
@ -12617,11 +12631,11 @@ as defined above.</p>
<p>Operation:</p> <p>Operation:</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p> <p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8; if (XLEN==32) bytes=4; else bytes=8;
@ -12639,11 +12653,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p> <p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp+=stack_adj;</code></pre> sp+=stack_adj;</code></pre>
</div> </div>
@ -12838,11 +12852,11 @@ switch (rlist) {
<p>Operation:</p> <p>Operation:</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p> <p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8; if (XLEN==32) bytes=4; else bytes=8;
@ -12860,7 +12874,7 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p> <p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div> </div>
<div class="admonitionblock note"> <div class="admonitionblock note">
<table> <table>
@ -12878,7 +12892,7 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
asm("li a0, 0"); asm("li a0, 0");
sp+=stack_adj; sp+=stack_adj;
@ -13078,11 +13092,11 @@ switch (rlist) {
<p>Operation:</p> <p>Operation:</p>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p> <p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8; if (XLEN==32) bytes=4; else bytes=8;
@ -13100,11 +13114,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div> </div>
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p> <p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp+=stack_adj; sp+=stack_adj;
asm("ret");</code></pre> asm("ret");</code></pre>
@ -13163,7 +13177,7 @@ The execution is atomic, so it is not possible to observe state where only one o
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space. <p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space.
The mapping between them is specified in the pseudo-code below.</p> The mapping between them is specified in the pseudocode below.</p>
</div> </div>
<div class="admonitionblock note"> <div class="admonitionblock note">
<table> <table>
@ -13196,7 +13210,7 @@ The mapping between them is specified in the pseudo-code below.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) { if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) {
reserved(); reserved();
} }
@ -13245,7 +13259,7 @@ The execution is atomic, so it is not possible to observe state where only one o
</div> </div>
<div class="paragraph"> <div class="paragraph">
<p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space. <p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space.
The mapping between them is specified in the pseudo-code below.</p> The mapping between them is specified in the pseudocode below.</p>
</div> </div>
<div class="admonitionblock note"> <div class="admonitionblock note">
<table> <table>
@ -13278,7 +13292,7 @@ The mapping between them is specified in the pseudo-code below.</p>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) { if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) {
reserved(); reserved();
} }
@ -13559,7 +13573,7 @@ attempt to program different modes and read back the values to see which are ava
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
# target_address is temporary internal state, it doesn't represent a real register # target_address is temporary internal state, it doesn't represent a real register
# InstMemory is byte indexed # InstMemory is byte indexed
@ -13662,7 +13676,7 @@ j target_address[XLEN-1:0]&amp;~0x1;</code></pre>
</div> </div>
<div class="listingblock"> <div class="listingblock">
<div class="content"> <div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet. <pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
# target_address is temporary internal state, it doesn't represent a real register # target_address is temporary internal state, it doesn't represent a real register
# InstMemory is byte indexed # InstMemory is byte indexed
@ -20117,7 +20131,7 @@ categories: <em>standard</em> versus <em>non-standard</em>.</p>
<li> <li>
<p>A standard extension is one that is generally useful and that is <p>A standard extension is one that is generally useful and that is
designed to not conflict with any other standard extension. Currently, designed to not conflict with any other standard extension. Currently,
"MAFDQLCBTPV", described in other chapters of this manual, are either "MAFDQCBTPV", described in other chapters of this manual, are either
complete or planned standard extensions.</p> complete or planned standard extensions.</p>
</li> </li>
<li> <li>
@ -25208,7 +25222,7 @@ sizes. Misaligned accesses are broken up into single-byte accesses.</p>
semantics (RV64I and A), are integrated into the <code>rmem</code> exploration tool semantics (RV64I and A), are integrated into the <code>rmem</code> exploration tool
(<a href="https://github.com/rems-project/rmem" class="bare">github.com/rems-project/rmem</a>). <code>rmem</code> can explore litmus tests (<a href="https://github.com/rems-project/rmem" class="bare">github.com/rems-project/rmem</a>). <code>rmem</code> can explore litmus tests
(see <a href="#litmustests">Section A.2</a>) and small ELF binaries (see <a href="#litmustests">Section A.2</a>) and small ELF binaries
exhaustively, pseudo-randomly and interactively. In <code>rmem</code>, the ISA exhaustively, pseudorandomly and interactively. In <code>rmem</code>, the ISA
semantics is expressed explicitly in Sail (see semantics is expressed explicitly in Sail (see
<a href="https://github.com/rems-project/sail" class="bare">github.com/rems-project/sail</a> for the Sail language, and <a href="https://github.com/rems-project/sail" class="bare">github.com/rems-project/sail</a> for the Sail language, and
<a href="https://github.com/rems-project/sail-riscv" class="bare">github.com/rems-project/sail-riscv</a> for the RISC-V ISA model), <a href="https://github.com/rems-project/sail-riscv" class="bare">github.com/rems-project/sail-riscv</a> for the RISC-V ISA model),
@ -26896,7 +26910,7 @@ an external oracle that provides an opcode when given a memory location.</p>
</div> </div>
<div id="footer"> <div id="footer">
<div id="footer-text"> <div id="footer-text">
Version 20240612<br> Version 20240703<br>
</div> </div>
</div> </div>
</body> </body>

8
docs/riscv-isa/build.mk
View file

@ -22,19 +22,19 @@ setup:
cp -r src build/riscv-isa-manual cp -r src build/riscv-isa-manual
priv-pdf: setup priv-pdf: setup
cd build/riscv-isa-manual/build; make priv-pdf cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-privileged.pdf
cp ./build/riscv-isa-manual/build/riscv-privileged.pdf priv-isa-$(CONFIG).pdf cp ./build/riscv-isa-manual/build/riscv-privileged.pdf priv-isa-$(CONFIG).pdf
priv-html: setup priv-html: setup
cd build/riscv-isa-manual/build; make priv-html cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-privileged.html
cp ./build/riscv-isa-manual/build/riscv-privileged.html priv-isa-$(CONFIG).html cp ./build/riscv-isa-manual/build/riscv-privileged.html priv-isa-$(CONFIG).html
unpriv-pdf: setup unpriv-pdf: setup
cd build/riscv-isa-manual/build; make unpriv-pdf cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-unprivileged.pdf
cp ./build/riscv-isa-manual/build/riscv-unprivileged.pdf unpriv-isa-$(CONFIG).pdf cp ./build/riscv-isa-manual/build/riscv-unprivileged.pdf unpriv-isa-$(CONFIG).pdf
unpriv-html: setup unpriv-html: setup
cd build/riscv-isa-manual/build; make unpriv-html cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-unprivileged.html
cp ./build/riscv-isa-manual/build/riscv-unprivileged.html unpriv-isa-$(CONFIG).html cp ./build/riscv-isa-manual/build/riscv-unprivileged.html unpriv-isa-$(CONFIG).html
clean: clean:

2
docs/riscv-isa/riscv-isa-manual

@ -1 +1 @@
Subproject commit c8c8075a6a71be67ac723528070e3e50ff7586b2 Subproject commit ebf2e3a0b402cd56fd4b571b705b31f3be62c2cc

5
docs/riscv-isa/src/colophon.adoc
View file

@ -7,7 +7,7 @@
This document describes the RISC-V unprivileged architecture tailored for This document describes the RISC-V unprivileged architecture tailored for
OpenHW Group {ohg-config}. OpenHW Group {ohg-config}.
[.big]*_Preface to Document Version 20240612_* [.big]*_Preface to Document Version 20240703_*
This document describes the RISC-V unprivileged architecture. This document describes the RISC-V unprivileged architecture.
@ -41,6 +41,7 @@ h|Extension h|Version h|Status
|*A* |*2.1* |*Ratified* |*A* |*2.1* |*Ratified*
|*Zawrs* |*1.01* |*Ratified* |*Zawrs* |*1.01* |*Ratified*
|*Zacas* |*1.0* |*Ratifed* |*Zacas* |*1.0* |*Ratifed*
|*Zabha* |*1.0* |*Ratifed*
|*RVWMO* |*2.0* |*Ratified* |*RVWMO* |*2.0* |*Ratified*
|*Ztso* |*1.0* |*Ratified* |*Ztso* |*1.0* |*Ratified*
|*CMO* |*1.0* |*Ratified* |*CMO* |*1.0* |*Ratified*
@ -72,6 +73,8 @@ h|Extension h|Version h|Status
|*Zvksed* |*1.0* |*Ratified* |*Zvksed* |*1.0* |*Ratified*
|*Zvksh* |*1.0* |*Ratified* |*Zvksh* |*1.0* |*Ratified*
|*Zvkt* |*1.0* |*Ratified* |*Zvkt* |*1.0* |*Ratified*
|*Zicfiss* |*1.0* |*Ratified*
|*Zicfilp* |*1.0* |*Ratified*
|=== |===
The changes in this version of the document include: The changes in this version of the document include:

4
docs/riscv-isa/src/config_define.adoc
View file

@ -63,6 +63,10 @@ ifeval::[{RVZsmdbltrp} == true]
:RVZsmdbltrp-true: :RVZsmdbltrp-true:
endif::[] endif::[]
ifeval::[{RVZssdbltrp} == true]
:RVZssdbltrp-true:
endif::[]
ifeval::[{RVZicfilp} == true] ifeval::[{RVZicfilp} == true]
:RVZicfilp-true: :RVZicfilp-true:
endif::[] endif::[]

157
docs/riscv-isa/src/machine.adoc
View file

@ -487,75 +487,13 @@ endif::[]
ifdef::archi-default,XLEN-32[] ifdef::archi-default,XLEN-32[]
[[mstatusreg-rv32]] [[mstatusreg-rv32]]
.Machine-mode status (`mstatus`) register for RV32 .Machine-mode status (`mstatus`) register for RV32
[wavedrom, ,svg] include::images/wavedrom/mstatusreg-rv321.adoc[]
....
{reg: [
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SPIE'},
{bits: 1, name: 'UBE'},
{bits: 1, name: 'MPIE'},
{bits: 1, name: 'SPP'},
{bits: 2, name: 'VS[1:0]'},
{bits: 2, name: 'MPP[1:0]'},
{bits: 2, name: 'FS[1:0]'},
{bits: 2, name: 'XS[1:0]'},
{bits: 1, name: 'MPRV'},
{bits: 1, name: 'SUM'},
{bits: 1, name: 'MXR'},
{bits: 1, name: 'TVM'},
{bits: 1, name: 'TW'},
{bits: 1, name: 'TSR'},
{bits: 1, name: 'SPELP'},
{bits: 7, name: 'WPRI'},
{bits: 1, name: 'SD'},
], config:{lanes: 2, hspace:1024}}
....
endif::[] endif::[]
ifdef::archi-default,XLEN-64[] ifdef::archi-default,XLEN-64[]
[[mstatusreg]] [[mstatusreg]]
.Machine-mode status (`mstatus`) register for RV64 .Machine-mode status (`mstatus`) register for RV64
[wavedrom, ,svg] include::images/wavedrom/mstatusreg.adoc[]
....
{reg: [
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SPIE'},
{bits: 1, name: 'UBE'},
{bits: 1, name: 'MPIE'},
{bits: 1, name: 'SPP'},
{bits: 2, name: 'VS[1:0]'},
{bits: 2, name: 'MPP[1:0]'},
{bits: 2, name: 'FS[1:0]'},
{bits: 2, name: 'XS[1:0]'},
{bits: 1, name: 'MPRV'},
{bits: 1, name: 'SUM'},
{bits: 1, name: 'MXR'},
{bits: 1, name: 'TVM'},
{bits: 1, name: 'TW'},
{bits: 1, name: 'TSR'},
{bits: 1, name: 'SPELP'},
{bits: 8, name: 'WPRI'},
{bits: 2, name: 'UXL[1:0]'},
{bits: 2, name: 'SXL[1:0]'},
{bits: 1, name: 'SBE'},
{bits: 1, name: 'MBE'},
{bits: 1, name: 'GVA'},
{bits: 1, name: 'MPV'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MPELP'},
{bits: 1, name: 'MDT'},
{bits: 20, name: 'WPRI'},
{bits: 1, name: 'SD'},
], config:{lanes: 4, hspace:1024}}
....
endif::[] endif::[]
ifdef::archi-default[] ifdef::archi-default[]
@ -571,20 +509,7 @@ endif::[]
ifdef::archi-default,XLEN-32[] ifdef::archi-default,XLEN-32[]
[[mstatushreg]] [[mstatushreg]]
.Additional machine-mode status (`mstatush`) register for RV32. .Additional machine-mode status (`mstatush`) register for RV32.
[wavedrom, ,svg] include::images/wavedrom/mstatushreg.adoc[]
....
{reg: [
{bits: 4, name: 'WPRI'},
{bits: 1, name: 'SBE'},
{bits: 1, name: 'MBE'},
{bits: 1, name: 'GVA'},
{bits: 1, name: 'MPV'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MPELP'},
{bits: 1, name: 'MDT'},
{bits: 21, name: 'WPRI'},
], config:{lanes: 2, hspace:1024}}
....
endif::[] endif::[]
[[privstack]] [[privstack]]
@ -769,8 +694,8 @@ ifeval::[{note} == true]
[NOTE] [NOTE]
==== ====
The consequence of this specification is that on occurrence of double trap the The consequence of this specification is that on occurrence of double trap the
RNMI handler is not provided with information that a trap would report in the RNMI handler is not provided with information that a trap reports in the
`mtval` and the `mtval2` registers. This information, if needed, may be obtained `mtval` and the `mtval2` registers. This information, if needed, can be obtained
by the RNMI handler by decoding the instruction at the address in `mnepc` and by the RNMI handler by decoding the instruction at the address in `mnepc` and
examining its source register contents. examining its source register contents.
==== ====
@ -779,7 +704,7 @@ endif::[]
ifdef::archi-default,RVZsmdbltrp-true[] ifdef::archi-default,RVZsmdbltrp-true[]
* When the Smrnmi extension is not implemented, or if the Smrnmi extension is * When the Smrnmi extension is not implemented, or if the Smrnmi extension is
implemented and `mnstatus.NMIE` is 0, the hart enters a critical-error state implemented and `mnstatus.NMIE` is 0, the hart enters a critical-error state
without updating any architectural state including the `pc`. This state without updating any architectural state, including the `pc`. This state
involves ceasing execution, disabling all interrupts (including NMIs), and involves ceasing execution, disabling all interrupts (including NMIs), and
asserting a `critical-error` signal to the platform. asserting a `critical-error` signal to the platform.
endif::[] endif::[]
@ -787,14 +712,17 @@ endif::[]
ifeval::[{note} == true] ifeval::[{note} == true]
[NOTE] [NOTE]
==== ====
The actions performed by the platform on assertion of a `critical-error` signal The actions performed by the platform when a hart asserts a `critical-error` signal
by a hart are platform specific. The range of possible actions include restarting are platform-specific. The range of possible actions include restarting
the affected hart or restarting the entire platform among others. the affected hart or restarting the entire platform, among others.
==== ====
endif::[] endif::[]
ifdef::archi-default,RVZsmdbltrp-true[] ifdef::archi-default,RVZsmdbltrp-true[]
An `MRET` instruction sets the `MDT` bit to 0. The `MRET` and `SRET` instructions, when executed in M-mode, set the `MDT` bit
to 0. If the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set
to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.
endif::[] endif::[]
ifndef::archi-default,RVZsmdbltrp-true[] ifndef::archi-default,RVZsmdbltrp-true[]
@ -862,6 +790,22 @@ ifndef::archi-default,RVS-true[]
[{ohg-config}] The SXL and UXL fields do not exist. [{ohg-config}] The SXL and UXL fields do not exist.
endif::[] endif::[]
ifdef::archi-default[]
Some HINT instructions are encoded as integer computational instructions that
overwrite their destination register with its current value, e.g.,
`c.addi x8, 0`.
When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the
destination register not all equal to bit XLEN-1, it is implementation-defined
whether bits MXLEN..XLEN of the destination register are unchanged or are
overwritten with copies of bit XLEN-1.
NOTE: This definition allows implementations to elide register writeback for
some HINTs, while allowing them to execute other HINTs in the same manner as
other integer computational instructions.
The implementation choice is observable only by privilege modes with an XLEN
setting greater than the current XLEN; it is invisible to the current
privilege mode.
endif::[]
===== Memory Privilege in `mstatus` Register ===== Memory Privilege in `mstatus` Register
@ -2912,28 +2856,10 @@ as shown in <<menvcfgreg>>, that controls
certain characteristics of the execution environment for modes less certain characteristics of the execution environment for modes less
privileged than M. privileged than M.
[#menvcfgreg] [[menvcfgreg]]
.Machine environment configuration (`menvcfg`) register. .Machine environment configuration (`menvcfg`) register.
[wavedrom, ,svg] include::images/wavedrom/menvcfgreg.adoc[]
....
{reg: [
{bits: 1, name: 'FIOM'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'LPE'},
{bits: 1, name: 'SSE'},
{bits: 2, name: 'CBIE'},
{bits: 1, name: 'CBCFE'},
{bits: 1, name: 'CBZE'},
{bits: 24, name: 'WPRI'},
{bits: 2, name: 'PMM'},
{bits: 25, name: 'WPRI'},
{bits: 1, name: 'DTE'},
{bits: 1, name: 'CDE'},
{bits: 1, name: 'ADUE'},
{bits: 1, name: 'PBMTE'},
{bits: 1, name: 'STCE'},
], config:{lanes: 4, hspace:1024}}
....
If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`, If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
FENCE instructions executed in modes less privileged than M are modified FENCE instructions executed in modes less privileged than M are modified
@ -3143,19 +3069,7 @@ shown in <<mseccfg>>, that controls security features.
[[mseccfg]] [[mseccfg]]
.Machine security configuration (`mseccfg`) register. .Machine security configuration (`mseccfg`) register.
[wavedrom, ,svg] include::images/wavedrom/mseccfg.adoc[]
....
{reg: [
{bits: 1, name: 'MML'},
{bits: 1, name: 'MMWP'},
{bits: 1, name: 'RLB'},
{bits: 5, name: 'WPRI'},
{bits: 1, name: 'USEED'},
{bits: 1, name: 'SSEED'},
{bits: 1, name: 'MLPE'},
{bits: 53, name: 'WPRI'},
], config:{lanes: 4, hspace:1024}}
....
The definitions of the SSEED and USEED fields will be furnished by the The definitions of the SSEED and USEED fields will be furnished by the
forthcoming entropy-source extension, Zkr. Their allocations within forthcoming entropy-source extension, Zkr. Their allocations within
@ -3252,8 +3166,9 @@ counting and wall-clock time.
==== ====
endif::[] endif::[]
Writes to `mtime` and `mtimecmp` are guaranteed to be reflected in MTIP If the result of the comparison between `mtime` and `mtimecmp` changes, it is
eventually, but not necessarily immediately. guaranteed to be reflected in MTIP eventually, but not necessarily
immediately.
ifeval::[{note} == true] ifeval::[{note} == true]
[NOTE] [NOTE]

26
docs/riscv-isa/src/priv-preface.adoc
View file

@ -6,10 +6,10 @@
This document describes the RISC-V privileged architecture tailored for This document describes the RISC-V privileged architecture tailored for
OpenHW Group {ohg-config}. OpenHW Group {ohg-config}.
[.big]*_Preface to Version 20240612_* [.big]*_Preface to Version 20240703_*
This document describes the RISC-V privileged architecture. This This document describes the RISC-V privileged architecture. This
release, version 20240612, contains the following versions of the RISC-V ISA release, version 20240703, contains the following versions of the RISC-V ISA
modules: modules:
[%autowidth,float="center",align="center",cols="^,<,^",options="header",] [%autowidth,float="center",align="center",cols="^,<,^",options="header",]
@ -19,10 +19,10 @@ modules:
*Smstateen Extension* + *Smstateen Extension* +
*Smcsrind/Sscsrind Extension* + *Smcsrind/Sscsrind Extension* +
*Smepmp* + *Smepmp* +
**Smcntrpmf* + *Smcntrpmf* +
*Smrnmi Extension* + *Smrnmi Extension* +
*Smcdeleg* + *Smcdeleg* +
*Smdbltrp* + _Smdbltrp_ +
_Supervisor ISA_ + _Supervisor ISA_ +
*Svade Extension* + *Svade Extension* +
*Svnapot Extension* + *Svnapot Extension* +
@ -31,9 +31,10 @@ _Supervisor ISA_ +
*Svadu Extension* + *Svadu Extension* +
*Sstc* + *Sstc* +
*Sscofpmf* + *Sscofpmf* +
*Ssdbltrp* + _Ssdbltrp_ +
*Hypervisor ISA* + *Hypervisor ISA* +
_Shlcofideleg_ _Shlcofideleg_ +
*Svvptc*
|_1.13_ + |_1.13_ +
*1.0* + *1.0* +
@ -42,7 +43,7 @@ _Shlcofideleg_
*1.0* + *1.0* +
*1.0* + *1.0* +
*1.0* + *1.0* +
*1.0* + _1.0_ +
_1.13_ + _1.13_ +
*1.0* + *1.0* +
*1.0* + *1.0* +
@ -51,9 +52,10 @@ _1.13_ +
*1.0* + *1.0* +
*1.0* + *1.0* +
*1.0* + *1.0* +
_1.0_ +
*1.0* + *1.0* +
*1.0* + _0.1_ +
_0.1_ *1.0*
|_Draft_ + |_Draft_ +
*Ratified* + *Ratified* +
@ -73,7 +75,8 @@ _Draft_ +
*Ratified* + *Ratified* +
_Draft_ + _Draft_ +
*Ratified* + *Ratified* +
_Draft_ _Draft_ +
*Ratified*
|=== |===
The following changes have been made since version 1.12 of the Machine and The following changes have been made since version 1.12 of the Machine and
@ -98,6 +101,7 @@ implemented.
* Specified synchronization requirements when changing the PBMTE fields * Specified synchronization requirements when changing the PBMTE fields
in `menvcfg` and `henvcfg`. in `menvcfg` and `henvcfg`.
* Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension. * Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension.
* Relaxed behavior of some HINTs when MXLEN > XLEN.
Finally, the following clarifications and document improvments have been made Finally, the following clarifications and document improvments have been made
since the last document release: since the last document release:
@ -117,6 +121,8 @@ be set to a nonzero value but sometimes not.
* Clarified exception behavior of unimplemented or inaccessible CSRs. * Clarified exception behavior of unimplemented or inaccessible CSRs.
* Clarified that Svpbmt allows implementations to override additional PMAs. * Clarified that Svpbmt allows implementations to override additional PMAs.
* Replaced the concept of vacant memory regions with inaccessible memory or I/O regions. * Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.
* Clarified that timer and count-overflow interrupts' arrival in
interrupt-pending registers is not immediate.
[.big]*_Preface to Version 20211203_* [.big]*_Preface to Version 20211203_*

15
docs/riscv-isa/src/riscv-privileged.adoc
View file

@ -2,23 +2,19 @@ include::config.adoc[]
[[risc-v-isa]] [[risc-v-isa]]
= The RISC-V Instruction Set Manual for {ohg-config}: Volume II: Privileged Architecture = The RISC-V Instruction Set Manual for {ohg-config}: Volume II: Privileged Architecture
include::../docs-resources/global-config.adoc[]
:description: Volume II - Privileged Architecture :description: Volume II - Privileged Architecture
:company: RISC-V.org :revnumber: 20240703
:revnumber: 20240612
//:revremark: Pre-release version //:revremark: Pre-release version
//development: assume everything can change //development: assume everything can change
//stable: assume everything could change //stable: assume everything could change
//frozen: of you implement this version you assume the risk that something might change because of the public review cycle but we expect little to no change. //frozen: of you implement this version you assume the risk that something might change because of the public review cycle but we expect little to no change.
//ratified: you can implement this and be assured nothing will change. if something needs to change due to an errata or enhancement, it will come out in a new extension. we do not revise extensions. //ratified: you can implement this and be assured nothing will change. if something needs to change due to an errata or enhancement, it will come out in a new extension. we do not revise extensions.
:url-riscv: http://riscv.org
:doctype: book
:colophon: :colophon:
:pdf-theme: ../src/resources/themes/riscv-spec.yml
:pdf-fontsdir: ../src/resources/fonts/
:preface-title: Preamble :preface-title: Preamble
:appendix-caption: Appendix :appendix-caption: Appendix
:imagesdir: images :imagesdir: ../docs-resources/images
:title-logo-image: image:risc-v_logo.png[pdfwidth=3.25in,align=center] :title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center]
:page-background-image: image:draft.png[opacity=20%] :page-background-image: image:draft.png[opacity=20%]
:title-page-background-image: image:ohg_logo.png[fit=none,pdfwidth=3.25in,position=top] :title-page-background-image: image:ohg_logo.png[fit=none,pdfwidth=3.25in,position=top]
//:title-page-background-image: none //:title-page-background-image: none
@ -27,7 +23,7 @@ include::config.adoc[]
:experimental: :experimental:
:reproducible: :reproducible:
:imagesoutdir: images :imagesoutdir: images
:bibtex-file: ../src/resources/riscv-spec.bib :bibtex-file: src/resources/riscv-spec.bib
:bibtex-order: alphabetical :bibtex-order: alphabetical
:bibtex-style: apa :bibtex-style: apa
:bibtex-format: asciidoc :bibtex-format: asciidoc
@ -61,6 +57,7 @@ endif::[]
:ne: &#8800; :ne: &#8800;
:approx: &#8776; :approx: &#8776;
:inf: &#8734; :inf: &#8734;
:imagesdir: images
This document describes the RISC-V privileged architecture tailored for This document describes the RISC-V privileged architecture tailored for
OpenHW Group {ohg-config}. OpenHW Group {ohg-config}.

17
docs/riscv-isa/src/riscv-unprivileged.adoc
View file

@ -2,19 +2,15 @@ include::config.adoc[]
[[risc-v-isa]] [[risc-v-isa]]
= The RISC-V Instruction Set Manual for {ohg-config}: Volume I - Unprivileged Architecture = The RISC-V Instruction Set Manual for {ohg-config}: Volume I - Unprivileged Architecture
:description: Volume I - Unprivileged Architecture include::../docs-resources/global-config.adoc[]
:company: RISC-V.org :description: Unprivileged Architecture
:revnumber: 20240612 :revnumber: 20240703
//:revremark: Pre-release version //:revremark: Pre-release version
:url-riscv: http://riscv.org
:doctype: book
:colophon: :colophon:
:pdf-theme: ../src/resources/themes/riscv-spec.yml
:pdf-fontsdir: ../src/resources/fonts/
:preface-title: Preamble :preface-title: Preamble
:appendix-caption: Appendix :appendix-caption: Appendix
:imagesdir: images :imagesdir: ../docs-resources/images
:title-logo-image: image:risc-v_logo.png[pdfwidth=3.25in,align=center] :title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center]
:page-background-image: image:draft.png[opacity=20%] :page-background-image: image:draft.png[opacity=20%]
:title-page-background-image: image:ohg_logo.png[fit=none,pdfwidth=3.25in,position=top] :title-page-background-image: image:ohg_logo.png[fit=none,pdfwidth=3.25in,position=top]
//:title-page-background-image: none //:title-page-background-image: none
@ -24,7 +20,7 @@ include::config.adoc[]
:experimental: :experimental:
:reproducible: :reproducible:
:imagesoutdir: images :imagesoutdir: images
:bibtex-file: ../src/resources/riscv-spec.bib :bibtex-file: src/resources/riscv-spec.bib
:bibtex-order: alphabetical :bibtex-order: alphabetical
:bibtex-style: apa :bibtex-style: apa
:bibtex-format: asciidoc :bibtex-format: asciidoc
@ -58,6 +54,7 @@ endif::[]
:approx: &#8776; :approx: &#8776;
:inf: &#8734; :inf: &#8734;
:csrname: envcfg :csrname: envcfg
:imagesdir: images
This document describes the RISC-V unprivileged architecture tailored for This document describes the RISC-V unprivileged architecture tailored for
OpenHW Group {ohg-config}. OpenHW Group {ohg-config}.

125
docs/riscv-isa/src/supervisor.adoc
View file

@ -88,7 +88,8 @@ ifdef::archi-default,XLEN-32[]
{bits: 1, name: 'MXR'}, {bits: 1, name: 'MXR'},
{bits: 3, name: 'WPRI'}, {bits: 3, name: 'WPRI'},
{bits: 1, name: 'SPELP'}, {bits: 1, name: 'SPELP'},
{bits: 7, name: 'WPRI'}, {bits: 1, name: 'SDT'},
{bits: 6, name: 'WPRI'},
{bits: 1, name: 'SD'}, {bits: 1, name: 'SD'},
], config:{lanes: 2, hspace:1024}} ], config:{lanes: 2, hspace:1024}}
.... ....
@ -116,7 +117,8 @@ ifdef::archi-default,XLEN-64[]
{bits: 1, name: 'MXR'}, {bits: 1, name: 'MXR'},
{bits: 3, name: 'WPRI'}, {bits: 3, name: 'WPRI'},
{bits: 1, name: 'SPELP'}, {bits: 1, name: 'SPELP'},
{bits: 8, name: 'WPRI'}, {bits: 1, name: 'SDT'},
{bits: 7, name: 'WPRI'},
{bits: 2, name: 'UXL[1:0]'}, {bits: 2, name: 'UXL[1:0]'},
{bits: 29, name: 'WPRI'}, {bits: 29, name: 'WPRI'},
{bits: 1, name: 'SD'}, {bits: 1, name: 'SD'},
@ -186,6 +188,22 @@ The effective XLEN in S-mode is termed _SXLEN_.
Its value is set to SXLEN=MXLEN. Its value is set to SXLEN=MXLEN.
endif::[] endif::[]
ifdef::archi-default[]
Some HINT instructions are encoded as integer computational instructions that
overwrite their destination register with its current value, e.g.,
`c.addi x8, 0`.
When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the
destination register not all equal to bit XLEN-1, it is implementation-defined
whether bits SXLEN..XLEN of the destination register are unchanged or are
overwritten with copies of bit XLEN-1.
NOTE: This definition allows implementations to elide register writeback for
some HINTs, while allowing them to execute other HINTs in the same manner as
other integer computational instructions.
The implementation choice is observable only by S-mode with SXLEN > UXLEN; it
is invisible to U-mode.
endif::[]
[[sum]] [[sum]]
===== Memory Privilege in `sstatus` Register ===== Memory Privilege in `sstatus` Register
@ -278,6 +296,70 @@ Access to the `SPELP` field, added by Zicfilp, accesses the homonymous
fields of `mstatus` when `V=0`, and the homonymous fields of `vsstatus` fields of `mstatus` when `V=0`, and the homonymous fields of `vsstatus`
when `V=1`. when `V=1`.
[[supv-double-trap]]
===== Double Trap Control in `sstatus` Register
ifdef::archi-default,RVZssdbltrp-true[]
The S-mode-disable-trap (`SDT`) bit is a WARL field introduced by the Ssdbltrp
extension to address double trap (See <<machine-double-trap>>) at privilege
modes lower than M.
When the `SDT` bit is set to 1 by an explicit CSR write, the `SIE` (Supervisor
Interrupt Enable) bit is cleared to 0. This clearing occurs regardless of the
value written, if any, to the `SIE` bit by the same write. The `SIE` bit can
only be set to 1 by an explicit CSR write if the `SDT` bit is being set to 0 by
the same write or is already 0.
When a trap is to be taken into S-mode, if the `SDT` bit is currently 0,
it is then set to 1, and the trap is delivered as expected. However, if `SDT` is
already set to 1, then this is an _unexpected trap_. In the event of an
_unexpected trap_, a double-trap exception trap is delivered into M-mode. To
deliver this trap, the hart writes registers, except `mcause` and `mtval2`, with
the same information that the _unexpected trap_ would have written if it was
taken into M-mode. The `mtval2` register is then set to what would be otherwise
written into the `mcause` register by the _unexpected trap_. The `mcause`
register is set to 16, the double-trap exception code.
An `SRET` instruction sets the `SDT` bit to 0.
[NOTE]
====
After a trap handler has saved the state, such as `scause`, `sepc`,
and `stval`, needed for resuming from the trap and is reentrant, it
should clear the `SDT` bit.
Resetting the `SDT` by an `SRET` enables the trap handler to detect a double
trap that may occur during the tail phase, where it restores critical state
to return from a trap.
The consequence of this specification is that if a critical error condition was
caused by a guest page-fault, then the GPA will not be available in `mtval2`
when the double trap is delivered to M-mode. This condition arises if the
HS-mode invokes a hypervisor virtual-machine load or store instruction when
`SDT` is 1 and the instruction raises a guest page-fault. The use of such an
instruction in this phase of trap handling is not common. However, not recording
the GPA is considered benign because, if required, it can still be obtained
-- albeit with added effort -- through the process of walking the page tables.
For a double trap that originates in VS-mode, M-mode should redirect the exception
to HS-mode by copying the values of M-mode CSRs updated by the trap to HS-mode
CSRs and should use an `MRET` to resume execution at the address in `stvec`.
Supervisor Software Events (SSE), an extension to the SBI, provide a
mechanism for supervisor software to register and service system events
emanating from an SBI implementation, such as firmware or a hypervisor. In the
event of a double trap, HS-mode and M-mode can utilize the SSE mechanism to
invoke a critical-error handler in VS-mode or S/HS-mode, respectively.
Additionally, the implementation of an SSE protocol can be considered as an
optional measure to aid in the recovery from such critical errors.
====
endif::[]
ifndef::archi-default,RVZssdbltrp-true[]
[{ohg-config}] As Double Trap Control (Ssdbltrp extension) is not implemented,
SDT field is read-only 0.
endif::[]
==== Supervisor Trap Vector Base Address (`stvec`) Register ==== Supervisor Trap Vector Base Address (`stvec`) Register
The `stvec` register is an SXLEN-bit read/write register that holds trap The `stvec` register is an SXLEN-bit read/write register that holds trap
@ -2511,31 +2593,34 @@ exceptions when A/D bits need be set, instead takes effect.
The Svade extension is also defined in <<translation>>. The Svade extension is also defined in <<translation>>.
[[sec:svvptc]] [[sec:svvptc]]
== "Svvptc" Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0 == "Svvptc" Extension for Obviating Memory-Management Instructions after Marking PTEs Valid, Version 1.0
When the Svvptc extension is implemented, explicit stores that update the Valid When the Svvptc extension is implemented, explicit stores by a hart that update
bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart
eventually become visible within a bounded timeframe to subsequent implicit will eventually become visible within a bounded timeframe to subsequent implicit
accesses by that hart to such PTEs. accesses by that hart to such PTEs.
endif::[] endif::[]
ifeval::[{note} == true] ifeval::[{note} == true]
[NOTE] [NOTE]
==== ====
Typically, PTEs are marked as Valid by the operating system following a Svvptc relieves an operating system from executing certain memory-management
page-fault exception or during system calls for memory mapping. In such cases, instructions, such as `SFENCE.VMA` or `SINVAL.VMA`, which would normally be used
the trap handler commonly employs an `SRET` instruction to return from the trap. to synchronize the hart's address-translation caches when a memory-resident PTE
When Svvptc is implemented, the stores it executes to change the Valid bit is changed from Invalid to Valid. Synchronizing the hart's address-translation
of the PTEs from 0 to 1 then become visible to implicit references to those PTEs caches with other forms of updates to a memory-resident PTE, including when a
within a bounded timeframe. This visibility pertains to the instructions like PTE is changed from Valid to Invalid, requires the use of suitable
the one causing the page fault or those accessing new memory regions. A memory-management instructions. Svvptc guarantees that a change to a PTE from
memory-management fence can be used to force immediate visibility of these PTE Invalid to Valid is made visible within a bounded time, thereby making the
updates to all implicit references associated with instructions following the execution of these memory-management instructions redundant. The performance
memory-management fence. However, when Svvptc is implemented, visibility (in a benefit of eliding these instructions outweighs the cost of an occasional
bounded amount of time) is guaranteed and use of a memory-management fence is gratuitous additional page fault that may occur.
not required in these scenarios. While this approach might lead to an occasional
gratuitous page-fault, the performance benefit of omitting the memory-management Depending on the microarchitecture, some possible ways to facilitate
fence instructions outweighs the occasional cost of a gratuitous page fault. implementation of Svvptc include: not having any address-translation caches, not
storing Invalid PTEs in the address-translation caches, automatically evicting
Invalid PTEs using a bounded timer, or making address-translation caches
coherent with store instructions that modify PTEs.
==== ====
endif::[] endif::[]