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update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 (#2323)

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since last riscv-isa-manual update (CVA6 commit 105d3601b):
- minor documentation changes
- use of docs-resources submodule inside riscv-isa-manual
- requires asciidoctor-lists
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André Sintzoff 2024-07-05 12:06:16 +02:00 • committed by GitHub
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@ -5,7 +5,7 @@
<meta http-equiv="X-UA-Compatible" content="IE=edge">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<meta name="generator" content="Asciidoctor 2.0.22">
<meta name="description" content="Volume I - Unprivileged Architecture">
<meta name="description" content="Unprivileged Architecture">
<title>The RISC-V Instruction Set Manual for CV32A65X: Volume I - Unprivileged Architecture</title>
<link rel="stylesheet" href="https://fonts.googleapis.com/css?family=Open+Sans:300,300italic,400,400italic,600,600italic%7CNoto+Serif:400,400italic,700,700italic%7CDroid+Sans+Mono:400,700">
<style>
@ -440,7 +440,7 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
<div id="header">
<h1>The RISC-V Instruction Set Manual for CV32A65X: Volume I - Unprivileged Architecture</h1>
<div class="details">
<span id="revnumber">version 20240612</span>
<span id="revnumber">version 20240703</span>
</div>
<div id="toc" class="toc2">
<div id="toctitle">Table of Contents</div>
@ -1019,7 +1019,7 @@ Jean-Roch Coulon, André Sintzoff.</em></p>
OpenHW Group CV32A65X.</p>
</div>
<div class="paragraph">
<p><strong class="big"><em>Preface to Document Version 20240612</em></strong></p>
<p><strong class="big"><em>Preface to Document Version 20240703</em></strong></p>
</div>
<div class="paragraph">
<p>This document describes the RISC-V unprivileged architecture.</p>
@ -1138,6 +1138,11 @@ to change before ratification.</p>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zabha</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>RVWMO</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>2.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
@ -1292,6 +1297,16 @@ to change before ratification.</p>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zicfiss</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zicfilp</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
</tbody>
</table>
<div class="paragraph">
@ -10047,7 +10062,7 @@ Zcb can be implemented on <em>any</em> CPU as the instructions are 16-bit versio
<i class="fa icon-note" title="Note"></i>
</td>
<td class="content">
<em>c.sext.w</em> is a pseudo-instruction for <em>c.addiw rd, 0</em> (RV64)
<em>c.sext.w</em> is a pseudoinstruction for <em>c.addiw rd, 0</em> (RV64)
</td>
</tr>
</table>
@ -10503,7 +10518,7 @@ Zcmt is primarily targeted at embedded class CPUs due to implementation complexi
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre>
</div>
@ -10573,7 +10588,7 @@ X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div>
@ -10643,7 +10658,7 @@ X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div>
@ -10713,7 +10728,7 @@ X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre>
</div>
@ -10783,7 +10798,7 @@ mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c)</code></pre>
</div>
@ -11572,7 +11587,7 @@ It is implementation defined whether interrupts can also be taken during the seq
<div class="ulist">
<ul>
<li>
<p>A sequence of stores writing the bytes required by the pseudo-code</p>
<p>A sequence of stores writing the bytes required by the pseudocode</p>
<div class="ulist">
<ul>
<li>
@ -11654,7 +11669,7 @@ addi sp, sp, -64</code></pre>
<div class="ulist">
<ul>
<li>
<p>A sequence of loads reading the bytes required by the pseudo-code.</p>
<p>A sequence of loads reading the bytes required by the pseudocode.</p>
<div class="ulist">
<ul>
<li>
@ -12040,11 +12055,11 @@ as defined above.</p>
<p>Operation:</p>
</div>
<div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p>
<p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8;
@ -12062,11 +12077,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
</div>
<div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
<p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp-=stack_adj;</code></pre>
</div>
@ -12266,11 +12281,11 @@ as defined above.</p>
<p>Operation:</p>
</div>
<div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p>
<p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8;
@ -12288,11 +12303,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
</div>
<div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
<p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp+=stack_adj;</code></pre>
</div>
@ -12487,11 +12502,11 @@ switch (rlist) {
<p>Operation:</p>
</div>
<div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p>
<p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8;
@ -12509,7 +12524,7 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
</div>
<div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
<p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div>
<div class="admonitionblock note">
<table>
@ -12527,7 +12542,7 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
asm("li a0, 0");
sp+=stack_adj;
@ -12727,11 +12742,11 @@ switch (rlist) {
<p>Operation:</p>
</div>
<div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p>
<p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8;
@ -12749,11 +12764,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
</div>
<div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
<p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp+=stack_adj;
asm("ret");</code></pre>
@ -12812,7 +12827,7 @@ The execution is atomic, so it is not possible to observe state where only one o
</div>
<div class="paragraph">
<p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space.
The mapping between them is specified in the pseudo-code below.</p>
The mapping between them is specified in the pseudocode below.</p>
</div>
<div class="admonitionblock note">
<table>
@ -12845,7 +12860,7 @@ The mapping between them is specified in the pseudo-code below.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) {
reserved();
}
@ -12894,7 +12909,7 @@ The execution is atomic, so it is not possible to observe state where only one o
</div>
<div class="paragraph">
<p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space.
The mapping between them is specified in the pseudo-code below.</p>
The mapping between them is specified in the pseudocode below.</p>
</div>
<div class="admonitionblock note">
<table>
@ -12927,7 +12942,7 @@ The mapping between them is specified in the pseudo-code below.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) {
reserved();
}
@ -13208,7 +13223,7 @@ attempt to program different modes and read back the values to see which are ava
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
# target_address is temporary internal state, it doesn't represent a real register
# InstMemory is byte indexed
@ -13311,7 +13326,7 @@ j target_address[XLEN-1:0]&amp;~0x1;</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
# target_address is temporary internal state, it doesn't represent a real register
# InstMemory is byte indexed
@ -19545,7 +19560,7 @@ categories: <em>standard</em> versus <em>non-standard</em>.</p>
<li>
<p>A standard extension is one that is generally useful and that is
designed to not conflict with any other standard extension. Currently,
"MAFDQLCBTPV", described in other chapters of this manual, are either
"MAFDQCBTPV", described in other chapters of this manual, are either
complete or planned standard extensions.</p>
</li>
<li>
@ -24636,7 +24651,7 @@ sizes. Misaligned accesses are broken up into single-byte accesses.</p>
semantics (RV64I and A), are integrated into the <code>rmem</code> exploration tool
(<a href="https://github.com/rems-project/rmem" class="bare">github.com/rems-project/rmem</a>). <code>rmem</code> can explore litmus tests
(see <a href="#litmustests">Section A.2</a>) and small ELF binaries
exhaustively, pseudo-randomly and interactively. In <code>rmem</code>, the ISA
exhaustively, pseudorandomly and interactively. In <code>rmem</code>, the ISA
semantics is expressed explicitly in Sail (see
<a href="https://github.com/rems-project/sail" class="bare">github.com/rems-project/sail</a> for the Sail language, and
<a href="https://github.com/rems-project/sail-riscv" class="bare">github.com/rems-project/sail-riscv</a> for the RISC-V ISA model),
@ -26330,7 +26345,7 @@ not supported.</p>
</div>
<div id="footer">
<div id="footer-text">
Version 20240612<br>
Version 20240703<br>
</div>
</div>
</body>

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@ -4,26 +4,24 @@
<meta charset="UTF-8">
<meta http-equiv="X-UA-Compatible" content="IE=edge">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<meta name="generator" content="Asciidoctor 2.0.15">
<meta name="description" content="Volume I - Unprivileged Architecture">
<meta name="generator" content="Asciidoctor 2.0.22">
<meta name="description" content="Unprivileged Architecture">
<title>The RISC-V Instruction Set Manual for CV64A6_MMU: Volume I - Unprivileged Architecture</title>
<link rel="stylesheet" href="https://fonts.googleapis.com/css?family=Open+Sans:300,300italic,400,400italic,600,600italic%7CNoto+Serif:400,400italic,700,700italic%7CDroid+Sans+Mono:400,700">
<style>
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article,aside,details,figcaption,figure,footer,header,hgroup,main,nav,section{display:block}
audio,video{display:inline-block}
audio:not([controls]){display:none;height:0}
html{font-family:sans-serif;-ms-text-size-adjust:100%;-webkit-text-size-adjust:100%}
/*! Asciidoctor default stylesheet | MIT License | https://asciidoctor.org */
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/* @import "https://fonts.googleapis.com/css?family=Open+Sans:300,300italic,400,400italic,600,600italic%7CNoto+Serif:400,400italic,700,700italic%7CDroid+Sans+Mono:400,700"; */
html{font-family:sans-serif;-webkit-text-size-adjust:100%}
a{background:none}
a:focus{outline:thin dotted}
a:active,a:hover{outline:0}
h1{font-size:2em;margin:.67em 0}
abbr[title]{border-bottom:1px dotted}
b,strong{font-weight:bold}
abbr{font-size:.9em}
abbr[title]{cursor:help;border-bottom:1px dotted #dddddf;text-decoration:none}
dfn{font-style:italic}
hr{-moz-box-sizing:content-box;box-sizing:content-box;height:0}
hr{height:0}
mark{background:#ff0;color:#000}
code,kbd,pre,samp{font-family:monospace;font-size:1em}
pre{white-space:pre-wrap}
@ -35,20 +33,22 @@ sub{bottom:-.25em}
img{border:0}
svg:not(:root){overflow:hidden}
figure{margin:0}
audio,video{display:inline-block}
audio:not([controls]){display:none;height:0}
fieldset{border:1px solid silver;margin:0 2px;padding:.35em .625em .75em}
legend{border:0;padding:0}
button,input,select,textarea{font-family:inherit;font-size:100%;margin:0}
button,input{line-height:normal}
button,select{text-transform:none}
button,html input[type="button"],input[type="reset"],input[type="submit"]{-webkit-appearance:button;cursor:pointer}
button,html input[type=button],input[type=reset],input[type=submit]{-webkit-appearance:button;cursor:pointer}
button[disabled],html input[disabled]{cursor:default}
input[type="checkbox"],input[type="radio"]{box-sizing:border-box;padding:0}
input[type=checkbox],input[type=radio]{padding:0}
button::-moz-focus-inner,input::-moz-focus-inner{border:0;padding:0}
textarea{overflow:auto;vertical-align:top}
table{border-collapse:collapse;border-spacing:0}
*,*::before,*::after{-moz-box-sizing:border-box;-webkit-box-sizing:border-box;box-sizing:border-box}
*,::before,::after{box-sizing:border-box}
html,body{font-size:100%}
body{background:#fff;color:rgba(0,0,0,.8);padding:0;margin:0;font-family:"Noto Serif","DejaVu Serif",serif;font-weight:400;font-style:normal;line-height:1;position:relative;cursor:auto;tab-size:4;word-wrap:anywhere;-moz-osx-font-smoothing:grayscale;-webkit-font-smoothing:antialiased}
body{background:#fff;color:rgba(0,0,0,.8);padding:0;margin:0;font-family:"Noto Serif","DejaVu Serif",serif;line-height:1;position:relative;cursor:auto;-moz-tab-size:4;-o-tab-size:4;tab-size:4;word-wrap:anywhere;-moz-osx-font-smoothing:grayscale;-webkit-font-smoothing:antialiased}
a:hover{cursor:pointer}
img,object,embed{max-width:100%;height:auto}
object,embed{height:100%}
@ -68,7 +68,7 @@ div,dl,dt,dd,ul,ol,li,h1,h2,h3,#toctitle,.sidebarblock>.content>.title,h4,h5,h6,
a{color:#2156a5;text-decoration:underline;line-height:inherit}
a:hover,a:focus{color:#1d4b8f}
a img{border:0}
p{font-family:inherit;font-weight:400;font-size:1em;line-height:1.6;margin-bottom:1.25em;text-rendering:optimizeLegibility}
p{line-height:1.6;margin-bottom:1.25em;text-rendering:optimizeLegibility}
p aside{font-size:.875em;line-height:1.35;font-style:italic}
h1,h2,h3,#toctitle,.sidebarblock>.content>.title,h4,h5,h6{font-family:"Open Sans","DejaVu Sans",sans-serif;font-weight:300;font-style:normal;color:#ba3925;text-rendering:optimizeLegibility;margin-top:1em;margin-bottom:.5em;line-height:1.0125em}
h1 small,h2 small,h3 small,#toctitle small,.sidebarblock>.content>.title small,h4 small,h5 small,h6 small{font-size:60%;color:#e99b8f;line-height:0}
@ -77,23 +77,21 @@ h2{font-size:1.6875em}
h3,#toctitle,.sidebarblock>.content>.title{font-size:1.375em}
h4,h5{font-size:1.125em}
h6{font-size:1em}
hr{border:solid #dddddf;border-width:1px 0 0;clear:both;margin:1.25em 0 1.1875em;height:0}
hr{border:solid #dddddf;border-width:1px 0 0;clear:both;margin:1.25em 0 1.1875em}
em,i{font-style:italic;line-height:inherit}
strong,b{font-weight:bold;line-height:inherit}
small{font-size:60%;line-height:inherit}
code{font-family:"Droid Sans Mono","DejaVu Sans Mono",monospace;font-weight:400;color:rgba(0,0,0,.9)}
ul,ol,dl{font-size:1em;line-height:1.6;margin-bottom:1.25em;list-style-position:outside;font-family:inherit}
ul,ol,dl{line-height:1.6;margin-bottom:1.25em;list-style-position:outside;font-family:inherit}
ul,ol{margin-left:1.5em}
ul li ul,ul li ol{margin-left:1.25em;margin-bottom:0;font-size:1em}
ul.square li ul,ul.circle li ul,ul.disc li ul{list-style:inherit}
ul.square{list-style-type:square}
ul li ul,ul li ol{margin-left:1.25em;margin-bottom:0}
ul.circle{list-style-type:circle}
ul.disc{list-style-type:disc}
ul.square{list-style-type:square}
ul.circle ul:not([class]),ul.disc ul:not([class]),ul.square ul:not([class]){list-style:inherit}
ol li ul,ol li ol{margin-left:1.25em;margin-bottom:0}
dl dt{margin-bottom:.3125em;font-weight:bold}
dl dd{margin-bottom:1.25em}
abbr,acronym{text-transform:uppercase;font-size:90%;color:rgba(0,0,0,.8);border-bottom:1px dotted #ddd;cursor:help}
abbr{text-transform:none}
blockquote{margin:0 0 1.25em;padding:.5625em 1.25em 0 1.1875em;border-left:1px solid #ddd}
blockquote,blockquote p{line-height:1.6;color:rgba(0,0,0,.85)}
@media screen and (min-width:768px){h1,h2,h3,#toctitle,.sidebarblock>.content>.title,h4,h5,h6{line-height:1.2}
@ -101,7 +99,7 @@ h1{font-size:2.75em}
h2{font-size:2.3125em}
h3,#toctitle,.sidebarblock>.content>.title{font-size:1.6875em}
h4{font-size:1.4375em}}
table{background:#fff;margin-bottom:1.25em;border:solid 1px #dedede;word-wrap:normal}
table{background:#fff;margin-bottom:1.25em;border:1px solid #dedede;word-wrap:normal}
table thead,table tfoot{background:#f7f8f7}
table thead tr th,table thead tr td,table tfoot tr th,table tfoot tr td{padding:.5em .625em .625em;font-size:inherit;color:rgba(0,0,0,.8);text-align:left}
table tr th,table tr td{padding:.5625em .625em;font-size:inherit;color:rgba(0,0,0,.8)}
@ -116,7 +114,7 @@ h1 strong,h2 strong,h3 strong,#toctitle strong,.sidebarblock>.content>.title str
:not(pre).nobreak{word-wrap:normal}
:not(pre).nowrap{white-space:nowrap}
:not(pre).pre-wrap{white-space:pre-wrap}
:not(pre):not([class^=L])>code{font-size:.9375em;font-style:normal!important;letter-spacing:0;padding:.1em .5ex;word-spacing:-.15em;background:#f7f7f8;-webkit-border-radius:4px;border-radius:4px;line-height:1.45;text-rendering:optimizeSpeed}
:not(pre):not([class^=L])>code{font-size:.9375em;font-style:normal!important;letter-spacing:0;padding:.1em .5ex;word-spacing:-.15em;background:#f7f7f8;border-radius:4px;line-height:1.45;text-rendering:optimizeSpeed}
pre{color:rgba(0,0,0,.9);font-family:"Droid Sans Mono","DejaVu Sans Mono",monospace;line-height:1.45;text-rendering:optimizeSpeed}
pre code,pre pre{color:inherit;font-size:inherit;line-height:inherit}
pre>code{display:block}
@ -124,7 +122,7 @@ pre.nowrap,pre.nowrap pre{white-space:pre;word-wrap:normal}
em em{font-style:normal}
strong strong{font-weight:400}
.keyseq{color:rgba(51,51,51,.8)}
kbd{font-family:"Droid Sans Mono","DejaVu Sans Mono",monospace;display:inline-block;color:rgba(0,0,0,.8);font-size:.65em;line-height:1.45;background:#f7f7f7;border:1px solid #ccc;-webkit-border-radius:3px;border-radius:3px;-webkit-box-shadow:0 1px 0 rgba(0,0,0,.2),0 0 0 .1em white inset;box-shadow:0 1px 0 rgba(0,0,0,.2),0 0 0 .1em #fff inset;margin:0 .15em;padding:.2em .5em;vertical-align:middle;position:relative;top:-.1em;white-space:nowrap}
kbd{font-family:"Droid Sans Mono","DejaVu Sans Mono",monospace;display:inline-block;color:rgba(0,0,0,.8);font-size:.65em;line-height:1.45;background:#f7f7f7;border:1px solid #ccc;border-radius:3px;box-shadow:0 1px 0 rgba(0,0,0,.2),inset 0 0 0 .1em #fff;margin:0 .15em;padding:.2em .5em;vertical-align:middle;position:relative;top:-.1em;white-space:nowrap}
.keyseq kbd:first-child{margin-left:0}
.keyseq kbd:last-child{margin-right:0}
.menuseq,.menuref{color:#000}
@ -136,15 +134,15 @@ b.button::before,b.button::after{position:relative;top:-1px;font-weight:400}
b.button::before{content:"[";padding:0 3px 0 2px}
b.button::after{content:"]";padding:0 2px 0 3px}
p a>code:hover{color:rgba(0,0,0,.9)}
#header,#content,#footnotes,#footer{width:100%;margin-left:auto;margin-right:auto;margin-top:0;margin-bottom:0;max-width:62.5em;*zoom:1;position:relative;padding-left:.9375em;padding-right:.9375em}
#header,#content,#footnotes,#footer{width:100%;margin:0 auto;max-width:62.5em;*zoom:1;position:relative;padding-left:.9375em;padding-right:.9375em}
#header::before,#header::after,#content::before,#content::after,#footnotes::before,#footnotes::after,#footer::before,#footer::after{content:" ";display:table}
#header::after,#content::after,#footnotes::after,#footer::after{clear:both}
#content{margin-top:1.25em}
#content::before{content:none}
#header>h1:first-child{color:rgba(0,0,0,.85);margin-top:2.25rem;margin-bottom:0}
#header>h1:first-child+#toc{margin-top:8px;border-top:1px solid #dddddf}
#header>h1:only-child,body.toc2 #header>h1:nth-last-child(2){border-bottom:1px solid #dddddf;padding-bottom:8px}
#header .details{border-bottom:1px solid #dddddf;line-height:1.45;padding-top:.25em;padding-bottom:.25em;padding-left:.25em;color:rgba(0,0,0,.6);display:-ms-flexbox;display:-webkit-flex;display:flex;-ms-flex-flow:row wrap;-webkit-flex-flow:row wrap;flex-flow:row wrap}
#header>h1:only-child{border-bottom:1px solid #dddddf;padding-bottom:8px}
#header .details{border-bottom:1px solid #dddddf;line-height:1.45;padding-top:.25em;padding-bottom:.25em;padding-left:.25em;color:rgba(0,0,0,.6);display:flex;flex-flow:row wrap}
#header .details span:first-child{margin-left:-.125em}
#header .details span.email a{color:rgba(0,0,0,.85)}
#header .details br{display:none}
@ -165,6 +163,7 @@ p a>code:hover{color:rgba(0,0,0,.9)}
#toctitle{color:#7a2518;font-size:1.2em}
@media screen and (min-width:768px){#toctitle{font-size:1.375em}
body.toc2{padding-left:15em;padding-right:0}
body.toc2 #header>h1:nth-last-child(2){border-bottom:1px solid #dddddf;padding-bottom:8px}
#toc.toc2{margin-top:0!important;background:#f8f8f7;position:fixed;width:15em;left:0;top:0;border-right:1px solid #e7e7e9;border-top-width:0!important;border-bottom-width:0!important;z-index:1000;padding:1.25em 1em;height:100%;overflow:auto}
#toc.toc2 #toctitle{margin-top:0;margin-bottom:.8rem;font-size:1.2em}
#toc.toc2>ul{font-size:.9em;margin-bottom:0}
@ -178,11 +177,11 @@ body.toc2.toc-right #toc.toc2{border-right-width:0;border-left:1px solid #e7e7e9
#toc.toc2>ul{font-size:.95em}
#toc.toc2 ul ul{padding-left:1.25em}
body.toc2.toc-right{padding-left:0;padding-right:20em}}
#content #toc{border-style:solid;border-width:1px;border-color:#e0e0dc;margin-bottom:1.25em;padding:1.25em;background:#f8f8f7;-webkit-border-radius:4px;border-radius:4px}
#content #toc{border:1px solid #e0e0dc;margin-bottom:1.25em;padding:1.25em;background:#f8f8f7;border-radius:4px}
#content #toc>:first-child{margin-top:0}
#content #toc>:last-child{margin-bottom:0}
#footer{max-width:none;background:rgba(0,0,0,.8);padding:1.25em}
#footer-text{color:rgba(255,255,255,.8);line-height:1.44}
#footer-text{color:hsla(0,0%,100%,.8);line-height:1.44}
#content{margin-bottom:.625em}
.sect1{padding-bottom:.625em}
@media screen and (min-width:768px){#content{margin-bottom:1.25em}
@ -195,29 +194,30 @@ body.toc2.toc-right{padding-left:0;padding-right:20em}}
#content h1>a.link,h2>a.link,h3>a.link,#toctitle>a.link,.sidebarblock>.content>.title>a.link,h4>a.link,h5>a.link,h6>a.link{color:#ba3925;text-decoration:none}
#content h1>a.link:hover,h2>a.link:hover,h3>a.link:hover,#toctitle>a.link:hover,.sidebarblock>.content>.title>a.link:hover,h4>a.link:hover,h5>a.link:hover,h6>a.link:hover{color:#a53221}
details,.audioblock,.imageblock,.literalblock,.listingblock,.stemblock,.videoblock{margin-bottom:1.25em}
details>summary:first-of-type{cursor:pointer;display:list-item;outline:none;margin-bottom:.75em}
details{margin-left:1.25rem}
details>summary{cursor:pointer;display:block;position:relative;line-height:1.6;margin-bottom:.625rem;outline:none;-webkit-tap-highlight-color:transparent}
details>summary::-webkit-details-marker{display:none}
details>summary::before{content:"";border:solid transparent;border-left:solid;border-width:.3em 0 .3em .5em;position:absolute;top:.5em;left:-1.25rem;transform:translateX(15%)}
details[open]>summary::before{border:solid transparent;border-top:solid;border-width:.5em .3em 0;transform:translateY(15%)}
details>summary::after{content:"";width:1.25rem;height:1em;position:absolute;top:.3em;left:-1.25rem}
.admonitionblock td.content>.title,.audioblock>.title,.exampleblock>.title,.imageblock>.title,.listingblock>.title,.literalblock>.title,.stemblock>.title,.openblock>.title,.paragraph>.title,.quoteblock>.title,table.tableblock>.title,.verseblock>.title,.videoblock>.title,.dlist>.title,.olist>.title,.ulist>.title,.qlist>.title,.hdlist>.title{text-rendering:optimizeLegibility;text-align:left;font-family:"Noto Serif","DejaVu Serif",serif;font-size:1rem;font-style:italic}
table.tableblock.fit-content>caption.title{white-space:nowrap;width:0}
.paragraph.lead>p,#preamble>.sectionbody>[class="paragraph"]:first-of-type p{font-size:1.21875em;line-height:1.6;color:rgba(0,0,0,.85)}
table.tableblock #preamble>.sectionbody>[class="paragraph"]:first-of-type p{font-size:inherit}
.paragraph.lead>p,#preamble>.sectionbody>[class=paragraph]:first-of-type p{font-size:1.21875em;line-height:1.6;color:rgba(0,0,0,.85)}
.admonitionblock>table{border-collapse:separate;border:0;background:none;width:100%}
.admonitionblock>table td.icon{text-align:center;width:80px}
.admonitionblock>table td.icon img{max-width:none}
.admonitionblock>table td.icon .title{font-weight:bold;font-family:"Open Sans","DejaVu Sans",sans-serif;text-transform:uppercase}
.admonitionblock>table td.content{padding-left:1.125em;padding-right:1.25em;border-left:1px solid #dddddf;color:rgba(0,0,0,.6);word-wrap:anywhere}
.admonitionblock>table td.content>:last-child>:last-child{margin-bottom:0}
.exampleblock>.content{border-style:solid;border-width:1px;border-color:#e6e6e6;margin-bottom:1.25em;padding:1.25em;background:#fff;-webkit-border-radius:4px;border-radius:4px}
.exampleblock>.content>:first-child{margin-top:0}
.exampleblock>.content>:last-child{margin-bottom:0}
.sidebarblock{border-style:solid;border-width:1px;border-color:#dbdbd6;margin-bottom:1.25em;padding:1.25em;background:#f3f3f2;-webkit-border-radius:4px;border-radius:4px}
.sidebarblock>:first-child{margin-top:0}
.sidebarblock>:last-child{margin-bottom:0}
.exampleblock>.content{border:1px solid #e6e6e6;margin-bottom:1.25em;padding:1.25em;background:#fff;border-radius:4px}
.sidebarblock{border:1px solid #dbdbd6;margin-bottom:1.25em;padding:1.25em;background:#f3f3f2;border-radius:4px}
.sidebarblock>.content>.title{color:#7a2518;margin-top:0;text-align:center}
.exampleblock>.content>:last-child>:last-child,.exampleblock>.content .olist>ol>li:last-child>:last-child,.exampleblock>.content .ulist>ul>li:last-child>:last-child,.exampleblock>.content .qlist>ol>li:last-child>:last-child,.sidebarblock>.content>:last-child>:last-child,.sidebarblock>.content .olist>ol>li:last-child>:last-child,.sidebarblock>.content .ulist>ul>li:last-child>:last-child,.sidebarblock>.content .qlist>ol>li:last-child>:last-child{margin-bottom:0}
.literalblock pre,.listingblock>.content>pre{-webkit-border-radius:4px;border-radius:4px;overflow-x:auto;padding:1em;font-size:.8125em}
.exampleblock>.content>:first-child,.sidebarblock>.content>:first-child{margin-top:0}
.exampleblock>.content>:last-child,.exampleblock>.content>:last-child>:last-child,.exampleblock>.content .olist>ol>li:last-child>:last-child,.exampleblock>.content .ulist>ul>li:last-child>:last-child,.exampleblock>.content .qlist>ol>li:last-child>:last-child,.sidebarblock>.content>:last-child,.sidebarblock>.content>:last-child>:last-child,.sidebarblock>.content .olist>ol>li:last-child>:last-child,.sidebarblock>.content .ulist>ul>li:last-child>:last-child,.sidebarblock>.content .qlist>ol>li:last-child>:last-child{margin-bottom:0}
.literalblock pre,.listingblock>.content>pre{border-radius:4px;overflow-x:auto;padding:1em;font-size:.8125em}
@media screen and (min-width:768px){.literalblock pre,.listingblock>.content>pre{font-size:.90625em}}
@media screen and (min-width:1280px){.literalblock pre,.listingblock>.content>pre{font-size:1em}}
.literalblock pre,.listingblock>.content>pre:not(.highlight),.listingblock>.content>pre[class="highlight"],.listingblock>.content>pre[class^="highlight "]{background:#f7f7f8}
.literalblock pre,.listingblock>.content>pre:not(.highlight),.listingblock>.content>pre[class=highlight],.listingblock>.content>pre[class^="highlight "]{background:#f7f7f8}
.literalblock.output pre{color:#f7f7f8;background:rgba(0,0,0,.9)}
.listingblock>.content{position:relative}
.listingblock code[data-lang]::before{display:none;content:attr(data-lang);position:absolute;font-size:.75em;top:.425rem;right:.5rem;line-height:1;text-transform:uppercase;color:inherit;opacity:.5}
@ -225,7 +225,7 @@ table.tableblock #preamble>.sectionbody>[class="paragraph"]:first-of-type p{font
.listingblock.terminal pre .command::before{content:attr(data-prompt);padding-right:.5em;color:inherit;opacity:.5}
.listingblock.terminal pre .command:not([data-prompt])::before{content:"$"}
.listingblock pre.highlightjs{padding:0}
.listingblock pre.highlightjs>code{padding:1em;-webkit-border-radius:4px;border-radius:4px}
.listingblock pre.highlightjs>code{padding:1em;border-radius:4px}
.listingblock pre.prettyprint{border-width:0}
.prettyprint{background:#f7f7f8}
pre.prettyprint .linenums{line-height:1.45;margin-left:2em}
@ -235,9 +235,8 @@ pre.prettyprint li:not(:first-child) code[data-lang]::before{display:none}
table.linenotable{border-collapse:separate;border:0;margin-bottom:0;background:none}
table.linenotable td[class]{color:inherit;vertical-align:top;padding:0;line-height:inherit;white-space:normal}
table.linenotable td.code{padding-left:.75em}
table.linenotable td.linenos{border-right:1px solid currentColor;opacity:.35;padding-right:.5em}
pre.pygments .lineno{border-right:1px solid currentColor;opacity:.35;display:inline-block;margin-right:.75em}
pre.pygments .lineno::before{content:"";margin-right:-.125em}
table.linenotable td.linenos,pre.pygments .linenos{border-right:1px solid;opacity:.35;padding-right:.5em;-webkit-user-select:none;-moz-user-select:none;-ms-user-select:none;user-select:none}
pre.pygments span.linenos{display:inline-block;margin-right:.75em}
.quoteblock{margin:0 1em 1.25em 1.5em;display:table}
.quoteblock:not(.excerpt)>.title{margin-left:-1.5em;margin-bottom:.75em}
.quoteblock blockquote,.quoteblock p{color:rgba(0,0,0,.85);font-size:1.15rem;line-height:1.75;word-spacing:.1em;letter-spacing:0;font-style:italic;text-align:justify}
@ -246,7 +245,7 @@ pre.pygments .lineno::before{content:"";margin-right:-.125em}
.quoteblock blockquote>.paragraph:last-child p{margin-bottom:0}
.quoteblock .attribution{margin-top:.75em;margin-right:.5ex;text-align:right}
.verseblock{margin:0 1em 1.25em}
.verseblock pre{font-family:"Open Sans","DejaVu Sans",sans;font-size:1.15rem;color:rgba(0,0,0,.85);font-weight:300;text-rendering:optimizeLegibility}
.verseblock pre{font-family:"Open Sans","DejaVu Sans",sans-serif;font-size:1.15rem;color:rgba(0,0,0,.85);font-weight:300;text-rendering:optimizeLegibility}
.verseblock pre strong{font-weight:400}
.verseblock .attribution{margin-top:1.25rem;margin-left:.5ex}
.quoteblock .attribution,.verseblock .attribution{font-size:.9375em;line-height:1.45;font-style:italic}
@ -274,7 +273,7 @@ table.frame-none>colgroup+*>:first-child>*,table.frame-sides>colgroup+*>:first-c
table.frame-none>:last-child>:last-child>*,table.frame-sides>:last-child>:last-child>*{border-bottom-width:0}
table.frame-none>*>tr>:first-child,table.frame-ends>*>tr>:first-child{border-left-width:0}
table.frame-none>*>tr>:last-child,table.frame-ends>*>tr>:last-child{border-right-width:0}
table.stripes-all tr,table.stripes-odd tr:nth-of-type(odd),table.stripes-even tr:nth-of-type(even),table.stripes-hover tr:hover{background:#f8f8f7}
table.stripes-all>*>tr,table.stripes-odd>*>tr:nth-of-type(odd),table.stripes-even>*>tr:nth-of-type(even),table.stripes-hover>*>tr:hover{background:#f8f8f7}
th.halign-left,td.halign-left{text-align:left}
th.halign-right,td.halign-right{text-align:right}
th.halign-center,td.halign-center{text-align:center}
@ -290,14 +289,15 @@ ol{margin-left:1.75em}
ul li ol{margin-left:1.5em}
dl dd{margin-left:1.125em}
dl dd:last-child,dl dd:last-child>:last-child{margin-bottom:0}
ol>li p,ul>li p,ul dd,ol dd,.olist .olist,.ulist .ulist,.ulist .olist,.olist .ulist{margin-bottom:.625em}
li p,ul dd,ol dd,.olist .olist,.ulist .ulist,.ulist .olist,.olist .ulist{margin-bottom:.625em}
ul.checklist,ul.none,ol.none,ul.no-bullet,ol.no-bullet,ol.unnumbered,ul.unstyled,ol.unstyled{list-style-type:none}
ul.no-bullet,ol.no-bullet,ol.unnumbered{margin-left:.625em}
ul.unstyled,ol.unstyled{margin-left:0}
ul.checklist{margin-left:.625em}
ul.checklist li>p:first-child>.fa-square-o:first-child,ul.checklist li>p:first-child>.fa-check-square-o:first-child{width:1.25em;font-size:.8em;position:relative;bottom:.125em}
ul.checklist li>p:first-child>input[type="checkbox"]:first-child{margin-right:.25em}
ul.inline{display:-ms-flexbox;display:-webkit-box;display:flex;-ms-flex-flow:row wrap;-webkit-flex-flow:row wrap;flex-flow:row wrap;list-style:none;margin:0 0 .625em -1.25em}
li>p:empty:only-child::before{content:"";display:inline-block}
ul.checklist>li>p:first-child{margin-left:-1em}
ul.checklist>li>p:first-child>.fa-square-o:first-child,ul.checklist>li>p:first-child>.fa-check-square-o:first-child{width:1.25em;font-size:.8em;position:relative;bottom:.125em}
ul.checklist>li>p:first-child>input[type=checkbox]:first-child{margin-right:.25em}
ul.inline{display:flex;flex-flow:row wrap;list-style:none;margin:0 0 .625em -1.25em}
ul.inline>li{margin-left:1.25em}
.unstyled dl dt{font-weight:400;font-style:normal}
ol.arabic{list-style-type:decimal}
@ -316,7 +316,7 @@ td.hdlist2{word-wrap:anywhere}
.colist td:not([class]):first-child{padding:.4em .75em 0;line-height:1;vertical-align:top}
.colist td:not([class]):first-child img{max-width:none}
.colist td:not([class]):last-child{padding:.25em 0}
.thumb,.th{line-height:0;display:inline-block;border:solid 4px #fff;-webkit-box-shadow:0 0 0 1px #ddd;box-shadow:0 0 0 1px #ddd}
.thumb,.th{line-height:0;display:inline-block;border:4px solid #fff;box-shadow:0 0 0 1px #ddd}
.imageblock.left{margin:.25em .625em 1.25em 0}
.imageblock.right{margin:.25em 0 1.25em .625em}
.imageblock>.title{margin-bottom:0}
@ -329,15 +329,13 @@ a.image{text-decoration:none;display:inline-block}
a.image object{pointer-events:none}
sup.footnote,sup.footnoteref{font-size:.875em;position:static;vertical-align:super}
sup.footnote a,sup.footnoteref a{text-decoration:none}
sup.footnote a:active,sup.footnoteref a:active{text-decoration:underline}
sup.footnote a:active,sup.footnoteref a:active,#footnotes .footnote a:first-of-type:active{text-decoration:underline}
#footnotes{padding-top:.75em;padding-bottom:.75em;margin-bottom:.625em}
#footnotes hr{width:20%;min-width:6.25em;margin:-.25em 0 .75em;border-width:1px 0 0}
#footnotes .footnote{padding:0 .375em 0 .225em;line-height:1.3334;font-size:.875em;margin-left:1.2em;margin-bottom:.2em}
#footnotes .footnote a:first-of-type{font-weight:bold;text-decoration:none;margin-left:-1.05em}
#footnotes .footnote:last-of-type{margin-bottom:0}
#content #footnotes{margin-top:-.625em;margin-bottom:0;padding:.75em 0}
.gist .file-data>table{border:0;background:#fff;width:100%;margin-bottom:0}
.gist .file-data>table td.line-data{width:99%}
div.unbreakable{page-break-inside:avoid}
.big{font-size:larger}
.small{font-size:smaller}
@ -384,7 +382,7 @@ a span.icon>.fa{cursor:inherit}
.admonitionblock td.icon .icon-warning::before{content:"\f071";color:#bf6900}
.admonitionblock td.icon .icon-caution::before{content:"\f06d";color:#bf3400}
.admonitionblock td.icon .icon-important::before{content:"\f06a";color:#bf0000}
.conum[data-value]{display:inline-block;color:#fff!important;background:rgba(0,0,0,.8);-webkit-border-radius:50%;border-radius:50%;text-align:center;font-size:.75em;width:1.67em;height:1.67em;line-height:1.67em;font-family:"Open Sans","DejaVu Sans",sans-serif;font-style:normal;font-weight:bold}
.conum[data-value]{display:inline-block;color:#fff!important;background:rgba(0,0,0,.8);border-radius:50%;text-align:center;font-size:.75em;width:1.67em;height:1.67em;line-height:1.67em;font-family:"Open Sans","DejaVu Sans",sans-serif;font-style:normal;font-weight:bold}
.conum[data-value] *{color:#fff!important}
.conum[data-value]+b{display:none}
.conum[data-value]::after{content:attr(data-value)}
@ -392,19 +390,20 @@ pre .conum[data-value]{position:relative;top:-.125em}
b.conum *{color:inherit!important}
.conum:not([data-value]):empty{display:none}
dt,th.tableblock,td.content,div.footnote{text-rendering:optimizeLegibility}
h1,h2,p,td.content,span.alt{letter-spacing:-.01em}
h1,h2,p,td.content,span.alt,summary{letter-spacing:-.01em}
p strong,td.content strong,div.footnote strong{letter-spacing:-.005em}
p,blockquote,dt,td.content,span.alt{font-size:1.0625rem}
p,blockquote,dt,td.content,td.hdlist1,span.alt,summary{font-size:1.0625rem}
p{margin-bottom:1.25rem}
.sidebarblock p,.sidebarblock dt,.sidebarblock td.content,p.tableblock{font-size:1em}
.exampleblock>.content{background:#fffef7;border-color:#e0e0dc;-webkit-box-shadow:0 1px 4px #e0e0dc;box-shadow:0 1px 4px #e0e0dc}
.exampleblock>.content{background:#fffef7;border-color:#e0e0dc;box-shadow:0 1px 4px #e0e0dc}
.print-only{display:none!important}
@page{margin:1.25cm .75cm}
@media print{*{-webkit-box-shadow:none!important;box-shadow:none!important;text-shadow:none!important}
@media print{*{box-shadow:none!important;text-shadow:none!important}
html{font-size:80%}
a{color:inherit!important;text-decoration:underline!important}
a.bare,a[href^="#"],a[href^="mailto:"]{text-decoration:none!important}
a[href^="http:"]:not(.bare)::after,a[href^="https:"]:not(.bare)::after{content:"(" attr(href) ")";display:inline-block;font-size:.875em;padding-left:.25em}
abbr[title]{border-bottom:1px dotted}
abbr[title]::after{content:" (" attr(title) ")"}
pre,blockquote,tr,img,object,svg{page-break-inside:avoid}
thead{display:table-header-group}
@ -428,7 +427,7 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
.print-only{display:block!important}
.hide-for-print{display:none!important}
.show-for-print{display:inherit!important}}
@media print,amzn-kf8{#header>h1:first-child{margin-top:1.25rem}
@media amzn-kf8,print{#header>h1:first-child{margin-top:1.25rem}
.sect1{padding:0!important}
.sect1+.sect1{border:0}
#footer{background:none}
@ -441,7 +440,7 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
<div id="header">
<h1>The RISC-V Instruction Set Manual for CV64A6_MMU: Volume I - Unprivileged Architecture</h1>
<div class="details">
<span id="revnumber">version 20240612</span>
<span id="revnumber">version 20240703</span>
</div>
<div id="toc" class="toc2">
<div id="toctitle">Table of Contents</div>
@ -1032,7 +1031,7 @@ Jean-Roch Coulon, André Sintzoff.</em></p>
OpenHW Group CV64A6_MMU.</p>
</div>
<div class="paragraph">
<p><strong class="big"><em>Preface to Document Version 20240612</em></strong></p>
<p><strong class="big"><em>Preface to Document Version 20240703</em></strong></p>
</div>
<div class="paragraph">
<p>This document describes the RISC-V unprivileged architecture.</p>
@ -1151,6 +1150,11 @@ to change before ratification.</p>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zabha</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratifed</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>RVWMO</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>2.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
@ -1305,6 +1309,16 @@ to change before ratification.</p>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zicfiss</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
<tr>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Zicfilp</strong></p></td>
<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.0</strong></p></td>
<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong></p></td>
</tr>
</tbody>
</table>
<div class="paragraph">
@ -10398,7 +10412,7 @@ Zcb can be implemented on <em>any</em> CPU as the instructions are 16-bit versio
<i class="fa icon-note" title="Note"></i>
</td>
<td class="content">
<em>c.sext.w</em> is a pseudo-instruction for <em>c.addiw rd, 0</em> (RV64)
<em>c.sext.w</em> is a pseudoinstruction for <em>c.addiw rd, 0</em> (RV64)
</td>
</tr>
</table>
@ -10854,7 +10868,7 @@ Zcmt is primarily targeted at embedded class CPUs due to implementation complexi
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre>
</div>
@ -10924,7 +10938,7 @@ X(rdc) = EXTZ(mem[X(rs1c)+EXTZ(uimm)][7..0]);</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div>
@ -10994,7 +11008,7 @@ X(rdc) = EXTZ(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div>
@ -11064,7 +11078,7 @@ X(rdc) = EXTS(load_mem[X(rs1c)+EXTZ(uimm)][15..0]);</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre>
</div>
@ -11134,7 +11148,7 @@ mem[X(rs1c)+EXTZ(uimm)][7..0] = X(rs2c)</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
mem[X(rs1c)+EXTZ(uimm)][15..0] = X(rs2c)</code></pre>
</div>
@ -11923,7 +11937,7 @@ It is implementation defined whether interrupts can also be taken during the seq
<div class="ulist">
<ul>
<li>
<p>A sequence of stores writing the bytes required by the pseudo-code</p>
<p>A sequence of stores writing the bytes required by the pseudocode</p>
<div class="ulist">
<ul>
<li>
@ -12005,7 +12019,7 @@ addi sp, sp, -64</code></pre>
<div class="ulist">
<ul>
<li>
<p>A sequence of loads reading the bytes required by the pseudo-code.</p>
<p>A sequence of loads reading the bytes required by the pseudocode.</p>
<div class="ulist">
<ul>
<li>
@ -12391,11 +12405,11 @@ as defined above.</p>
<p>Operation:</p>
</div>
<div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p>
<p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8;
@ -12413,11 +12427,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
</div>
<div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
<p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp-=stack_adj;</code></pre>
</div>
@ -12617,11 +12631,11 @@ as defined above.</p>
<p>Operation:</p>
</div>
<div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p>
<p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8;
@ -12639,11 +12653,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
</div>
<div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
<p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp+=stack_adj;</code></pre>
</div>
@ -12838,11 +12852,11 @@ switch (rlist) {
<p>Operation:</p>
</div>
<div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p>
<p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8;
@ -12860,7 +12874,7 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
</div>
<div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
<p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div>
<div class="admonitionblock note">
<table>
@ -12878,7 +12892,7 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
asm("li a0, 0");
sp+=stack_adj;
@ -13078,11 +13092,11 @@ switch (rlist) {
<p>Operation:</p>
</div>
<div class="paragraph">
<p>The first section of pseudo-code may be executed multiple times before the instruction successfully completes.</p>
<p>The first section of pseudocode may be executed multiple times before the instruction successfully completes.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (XLEN==32) bytes=4; else bytes=8;
@ -13100,11 +13114,11 @@ for(i in 27,26,25,24,23,22,21,20,19,18,9,8,1) {
</div>
</div>
<div class="paragraph">
<p>The final section of pseudo-code executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
<p>The final section of pseudocode executes atomically, and only executes if the section above completes without any exceptions or interrupts.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
sp+=stack_adj;
asm("ret");</code></pre>
@ -13163,7 +13177,7 @@ The execution is atomic, so it is not possible to observe state where only one o
</div>
<div class="paragraph">
<p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space.
The mapping between them is specified in the pseudo-code below.</p>
The mapping between them is specified in the pseudocode below.</p>
</div>
<div class="admonitionblock note">
<table>
@ -13196,7 +13210,7 @@ The mapping between them is specified in the pseudo-code below.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) {
reserved();
}
@ -13245,7 +13259,7 @@ The execution is atomic, so it is not possible to observe state where only one o
</div>
<div class="paragraph">
<p>The encoding uses <em>sreg</em> number specifiers instead of <em>xreg</em> number specifiers to save encoding space.
The mapping between them is specified in the pseudo-code below.</p>
The mapping between them is specified in the pseudocode below.</p>
</div>
<div class="admonitionblock note">
<table>
@ -13278,7 +13292,7 @@ The mapping between them is specified in the pseudo-code below.</p>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
if (RV32E &amp;&amp; (r1sc&gt;1 || r2sc&gt;1)) {
reserved();
}
@ -13559,7 +13573,7 @@ attempt to program different modes and read back the values to see which are ava
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
# target_address is temporary internal state, it doesn't represent a real register
# InstMemory is byte indexed
@ -13662,7 +13676,7 @@ j target_address[XLEN-1:0]&amp;~0x1;</code></pre>
</div>
<div class="listingblock">
<div class="content">
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
<pre class="pygments highlight"><code data-lang="sail">//This is not SAIL, it's pseudocode. The SAIL hasn't been written yet.
# target_address is temporary internal state, it doesn't represent a real register
# InstMemory is byte indexed
@ -20117,7 +20131,7 @@ categories: <em>standard</em> versus <em>non-standard</em>.</p>
<li>
<p>A standard extension is one that is generally useful and that is
designed to not conflict with any other standard extension. Currently,
"MAFDQLCBTPV", described in other chapters of this manual, are either
"MAFDQCBTPV", described in other chapters of this manual, are either
complete or planned standard extensions.</p>
</li>
<li>
@ -25208,7 +25222,7 @@ sizes. Misaligned accesses are broken up into single-byte accesses.</p>
semantics (RV64I and A), are integrated into the <code>rmem</code> exploration tool
(<a href="https://github.com/rems-project/rmem" class="bare">github.com/rems-project/rmem</a>). <code>rmem</code> can explore litmus tests
(see <a href="#litmustests">Section A.2</a>) and small ELF binaries
exhaustively, pseudo-randomly and interactively. In <code>rmem</code>, the ISA
exhaustively, pseudorandomly and interactively. In <code>rmem</code>, the ISA
semantics is expressed explicitly in Sail (see
<a href="https://github.com/rems-project/sail" class="bare">github.com/rems-project/sail</a> for the Sail language, and
<a href="https://github.com/rems-project/sail-riscv" class="bare">github.com/rems-project/sail-riscv</a> for the RISC-V ISA model),
@ -26896,7 +26910,7 @@ an external oracle that provides an opcode when given a memory location.</p>
</div>
<div id="footer">
<div id="footer-text">
Version 20240612<br>
Version 20240703<br>
</div>
</div>
</body>

8
docs/riscv-isa/build.mk
View file

@ -22,19 +22,19 @@ setup:
cp -r src build/riscv-isa-manual
priv-pdf: setup
cd build/riscv-isa-manual/build; make priv-pdf
cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-privileged.pdf
cp ./build/riscv-isa-manual/build/riscv-privileged.pdf priv-isa-$(CONFIG).pdf
priv-html: setup
cd build/riscv-isa-manual/build; make priv-html
cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-privileged.html
cp ./build/riscv-isa-manual/build/riscv-privileged.html priv-isa-$(CONFIG).html
unpriv-pdf: setup
cd build/riscv-isa-manual/build; make unpriv-pdf
cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-unprivileged.pdf
cp ./build/riscv-isa-manual/build/riscv-unprivileged.pdf unpriv-isa-$(CONFIG).pdf
unpriv-html: setup
cd build/riscv-isa-manual/build; make unpriv-html
cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-unprivileged.html
cp ./build/riscv-isa-manual/build/riscv-unprivileged.html unpriv-isa-$(CONFIG).html
clean:

2
docs/riscv-isa/riscv-isa-manual

@ -1 +1 @@
Subproject commit c8c8075a6a71be67ac723528070e3e50ff7586b2
Subproject commit ebf2e3a0b402cd56fd4b571b705b31f3be62c2cc

5
docs/riscv-isa/src/colophon.adoc
View file

@ -7,7 +7,7 @@
This document describes the RISC-V unprivileged architecture tailored for
OpenHW Group {ohg-config}.
[.big]*_Preface to Document Version 20240612_*
[.big]*_Preface to Document Version 20240703_*
This document describes the RISC-V unprivileged architecture.
@ -41,6 +41,7 @@ h|Extension h|Version h|Status
|*A* |*2.1* |*Ratified*
|*Zawrs* |*1.01* |*Ratified*
|*Zacas* |*1.0* |*Ratifed*
|*Zabha* |*1.0* |*Ratifed*
|*RVWMO* |*2.0* |*Ratified*
|*Ztso* |*1.0* |*Ratified*
|*CMO* |*1.0* |*Ratified*
@ -72,6 +73,8 @@ h|Extension h|Version h|Status
|*Zvksed* |*1.0* |*Ratified*
|*Zvksh* |*1.0* |*Ratified*
|*Zvkt* |*1.0* |*Ratified*
|*Zicfiss* |*1.0* |*Ratified*
|*Zicfilp* |*1.0* |*Ratified*
|===
The changes in this version of the document include:

4
docs/riscv-isa/src/config_define.adoc
View file

@ -63,6 +63,10 @@ ifeval::[{RVZsmdbltrp} == true]
:RVZsmdbltrp-true:
endif::[]
ifeval::[{RVZssdbltrp} == true]
:RVZssdbltrp-true:
endif::[]
ifeval::[{RVZicfilp} == true]
:RVZicfilp-true:
endif::[]

177
docs/riscv-isa/src/machine.adoc
View file

@ -487,75 +487,13 @@ endif::[]
ifdef::archi-default,XLEN-32[]
[[mstatusreg-rv32]]
.Machine-mode status (`mstatus`) register for RV32
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SPIE'},
{bits: 1, name: 'UBE'},
{bits: 1, name: 'MPIE'},
{bits: 1, name: 'SPP'},
{bits: 2, name: 'VS[1:0]'},
{bits: 2, name: 'MPP[1:0]'},
{bits: 2, name: 'FS[1:0]'},
{bits: 2, name: 'XS[1:0]'},
{bits: 1, name: 'MPRV'},
{bits: 1, name: 'SUM'},
{bits: 1, name: 'MXR'},
{bits: 1, name: 'TVM'},
{bits: 1, name: 'TW'},
{bits: 1, name: 'TSR'},
{bits: 1, name: 'SPELP'},
{bits: 7, name: 'WPRI'},
{bits: 1, name: 'SD'},
], config:{lanes: 2, hspace:1024}}
....
include::images/wavedrom/mstatusreg-rv321.adoc[]
endif::[]
ifdef::archi-default,XLEN-64[]
[[mstatusreg]]
.Machine-mode status (`mstatus`) register for RV64
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MIE'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'SPIE'},
{bits: 1, name: 'UBE'},
{bits: 1, name: 'MPIE'},
{bits: 1, name: 'SPP'},
{bits: 2, name: 'VS[1:0]'},
{bits: 2, name: 'MPP[1:0]'},
{bits: 2, name: 'FS[1:0]'},
{bits: 2, name: 'XS[1:0]'},
{bits: 1, name: 'MPRV'},
{bits: 1, name: 'SUM'},
{bits: 1, name: 'MXR'},
{bits: 1, name: 'TVM'},
{bits: 1, name: 'TW'},
{bits: 1, name: 'TSR'},
{bits: 1, name: 'SPELP'},
{bits: 8, name: 'WPRI'},
{bits: 2, name: 'UXL[1:0]'},
{bits: 2, name: 'SXL[1:0]'},
{bits: 1, name: 'SBE'},
{bits: 1, name: 'MBE'},
{bits: 1, name: 'GVA'},
{bits: 1, name: 'MPV'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MPELP'},
{bits: 1, name: 'MDT'},
{bits: 20, name: 'WPRI'},
{bits: 1, name: 'SD'},
], config:{lanes: 4, hspace:1024}}
....
include::images/wavedrom/mstatusreg.adoc[]
endif::[]
ifdef::archi-default[]
@ -571,20 +509,7 @@ endif::[]
ifdef::archi-default,XLEN-32[]
[[mstatushreg]]
.Additional machine-mode status (`mstatush`) register for RV32.
[wavedrom, ,svg]
....
{reg: [
{bits: 4, name: 'WPRI'},
{bits: 1, name: 'SBE'},
{bits: 1, name: 'MBE'},
{bits: 1, name: 'GVA'},
{bits: 1, name: 'MPV'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'MPELP'},
{bits: 1, name: 'MDT'},
{bits: 21, name: 'WPRI'},
], config:{lanes: 2, hspace:1024}}
....
include::images/wavedrom/mstatushreg.adoc[]
endif::[]
[[privstack]]
@ -769,8 +694,8 @@ ifeval::[{note} == true]
[NOTE]
====
The consequence of this specification is that on occurrence of double trap the
RNMI handler is not provided with information that a trap would report in the
`mtval` and the `mtval2` registers. This information, if needed, may be obtained
RNMI handler is not provided with information that a trap reports in the
`mtval` and the `mtval2` registers. This information, if needed, can be obtained
by the RNMI handler by decoding the instruction at the address in `mnepc` and
examining its source register contents.
====
@ -779,7 +704,7 @@ endif::[]
ifdef::archi-default,RVZsmdbltrp-true[]
* When the Smrnmi extension is not implemented, or if the Smrnmi extension is
implemented and `mnstatus.NMIE` is 0, the hart enters a critical-error state
without updating any architectural state including the `pc`. This state
without updating any architectural state, including the `pc`. This state
involves ceasing execution, disabling all interrupts (including NMIs), and
asserting a `critical-error` signal to the platform.
endif::[]
@ -787,14 +712,17 @@ endif::[]
ifeval::[{note} == true]
[NOTE]
====
The actions performed by the platform on assertion of a `critical-error` signal
by a hart are platform specific. The range of possible actions include restarting
the affected hart or restarting the entire platform among others.
The actions performed by the platform when a hart asserts a `critical-error` signal
are platform-specific. The range of possible actions include restarting
the affected hart or restarting the entire platform, among others.
====
endif::[]
ifdef::archi-default,RVZsmdbltrp-true[]
An `MRET` instruction sets the `MDT` bit to 0.
The `MRET` and `SRET` instructions, when executed in M-mode, set the `MDT` bit
to 0. If the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set
to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.
endif::[]
ifndef::archi-default,RVZsmdbltrp-true[]
@ -839,7 +767,7 @@ endif::[]
ifeval::["{ohg-config}" == "CV64A6_MMU"]
[{ohg-config}] The SXL and UXL fields are read-only fields that encode the
value of XLEN for S-mode and U-mode, respectively. The encoding of these
fields is the same as the MXL field of `misa`, shown in <<misabase>>.
fields is the same as the MXL field of `misa`, shown in <<misabase>>.
The effective XLEN in S-mode and U-mode are termed _SXLEN_ and _UXLEN_, respectively.
Their values are set to UXLEN=SXLEN=MXLEN.
endif::[]
@ -862,6 +790,22 @@ ifndef::archi-default,RVS-true[]
[{ohg-config}] The SXL and UXL fields do not exist.
endif::[]
ifdef::archi-default[]
Some HINT instructions are encoded as integer computational instructions that
overwrite their destination register with its current value, e.g.,
`c.addi x8, 0`.
When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the
destination register not all equal to bit XLEN-1, it is implementation-defined
whether bits MXLEN..XLEN of the destination register are unchanged or are
overwritten with copies of bit XLEN-1.
NOTE: This definition allows implementations to elide register writeback for
some HINTs, while allowing them to execute other HINTs in the same manner as
other integer computational instructions.
The implementation choice is observable only by privilege modes with an XLEN
setting greater than the current XLEN; it is invisible to the current
privilege mode.
endif::[]
===== Memory Privilege in `mstatus` Register
@ -873,7 +817,7 @@ protection mechanisms of the current privilege mode. When MPRV=1, load
and store memory addresses are translated and protected, and endianness
is applied, as though the current privilege mode were set to MPP.
Instruction address-translation and protection are unaffected by the
setting of MPRV.
setting of MPRV.
endif::[]
ifdef::archi-default[]
@ -891,7 +835,7 @@ loads access virtual memory. When MXR=0, only loads from pages marked
readable (R=1 in <<sv32pte>>) will succeed. When
MXR=1, loads from pages marked either readable or executable (R=1 or
X=1) will succeed. MXR has no effect when page-based virtual memory is
not in effect.
not in effect.
endif::[]
ifdef::archi-default[]
@ -921,11 +865,11 @@ SUM=0, S-mode memory accesses to pages that are accessible by U-mode
(U=1 in <<sv32pte>>) will fault. When SUM=1, these
accesses are permitted. SUM has no effect when page-based virtual memory
is not in effect. Note that, while SUM is ordinarily ignored when not
executing in S-mode, it _is_ in effect when MPRV=1 and MPP=S.
executing in S-mode, it _is_ in effect when MPRV=1 and MPP=S.
endif::[]
ifdef::archi-default[]
SUM is
SUM is
read-only 0 if S-mode is not supported or if `satp`.MODE is read-only 0.
endif::[]
@ -1087,10 +1031,10 @@ The TVM (Trap Virtual Memory) bit is a *WARL* field that supports intercepting
supervisor virtual-memory management operations. When TVM=1, attempts to
read or write the `satp` CSR or execute an SFENCE.VMA or SINVAL.VMA
instruction while executing in S-mode will raise an illegal-instruction
exception. When TVM=0, these operations are permitted in S-mode.
exception. When TVM=0, these operations are permitted in S-mode.
endif::[]
ifdef::archi-default[]
TVM is
TVM is
read-only 0 when S-mode is not supported.
endif::[]
@ -1125,7 +1069,7 @@ implementation-specific, bounded time limit, the WFI instruction causes
an illegal-instruction exception. An implementation may have WFI always
raise an illegal-instruction exception in less-privileged modes when
TW=1, even if there are pending globally-disabled interrupts when the
instruction is executed.
instruction is executed.
endif::[]
ifdef::archi-default[]
TW is read-only 0 when there are no modes less
@ -1161,7 +1105,7 @@ ifdef::archi-default,RVS-true[]
The TSR (Trap SRET) bit is a *WARL* field that supports intercepting the
supervisor exception return instruction, SRET. When TSR=1, attempts to
execute SRET while executing in S-mode will raise an illegal-instruction
exception. When TSR=0, this operation is permitted in S-mode.
exception. When TSR=0, this operation is permitted in S-mode.
endif::[]
ifdef::archi-default[]
TSR is
@ -2196,7 +2140,7 @@ counters, `mhpmcounter3`-`mhpmcounter31`. The event selector CSRs,
`mhpmevent3`-`mhpmevent31`, are 64-bit *WARL* registers that control which
event causes the corresponding counter to increment. The meaning of
these events is defined by the platform, but event 0 is defined to mean
"no event."
"no event."
endif::[]
ifdef::archi-default[]
@ -2912,28 +2856,10 @@ as shown in <<menvcfgreg>>, that controls
certain characteristics of the execution environment for modes less
privileged than M.
[#menvcfgreg]
[[menvcfgreg]]
.Machine environment configuration (`menvcfg`) register.
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'FIOM'},
{bits: 1, name: 'WPRI'},
{bits: 1, name: 'LPE'},
{bits: 1, name: 'SSE'},
{bits: 2, name: 'CBIE'},
{bits: 1, name: 'CBCFE'},
{bits: 1, name: 'CBZE'},
{bits: 24, name: 'WPRI'},
{bits: 2, name: 'PMM'},
{bits: 25, name: 'WPRI'},
{bits: 1, name: 'DTE'},
{bits: 1, name: 'CDE'},
{bits: 1, name: 'ADUE'},
{bits: 1, name: 'PBMTE'},
{bits: 1, name: 'STCE'},
], config:{lanes: 4, hspace:1024}}
....
include::images/wavedrom/menvcfgreg.adoc[]
If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
FENCE instructions executed in modes less privileged than M are modified
@ -3143,19 +3069,7 @@ shown in <<mseccfg>>, that controls security features.
[[mseccfg]]
.Machine security configuration (`mseccfg`) register.
[wavedrom, ,svg]
....
{reg: [
{bits: 1, name: 'MML'},
{bits: 1, name: 'MMWP'},
{bits: 1, name: 'RLB'},
{bits: 5, name: 'WPRI'},
{bits: 1, name: 'USEED'},
{bits: 1, name: 'SSEED'},
{bits: 1, name: 'MLPE'},
{bits: 53, name: 'WPRI'},
], config:{lanes: 4, hspace:1024}}
....
include::images/wavedrom/mseccfg.adoc[]
The definitions of the SSEED and USEED fields will be furnished by the
forthcoming entropy-source extension, Zkr. Their allocations within
@ -3252,8 +3166,9 @@ counting and wall-clock time.
====
endif::[]
Writes to `mtime` and `mtimecmp` are guaranteed to be reflected in MTIP
eventually, but not necessarily immediately.
If the result of the comparison between `mtime` and `mtimecmp` changes, it is
guaranteed to be reflected in MTIP eventually, but not necessarily
immediately.
ifeval::[{note} == true]
[NOTE]

26
docs/riscv-isa/src/priv-preface.adoc
View file

@ -6,10 +6,10 @@
This document describes the RISC-V privileged architecture tailored for
OpenHW Group {ohg-config}.
[.big]*_Preface to Version 20240612_*
[.big]*_Preface to Version 20240703_*
This document describes the RISC-V privileged architecture. This
release, version 20240612, contains the following versions of the RISC-V ISA
release, version 20240703, contains the following versions of the RISC-V ISA
modules:
[%autowidth,float="center",align="center",cols="^,<,^",options="header",]
@ -19,10 +19,10 @@ modules:
*Smstateen Extension* +
*Smcsrind/Sscsrind Extension* +
*Smepmp* +
**Smcntrpmf* +
*Smcntrpmf* +
*Smrnmi Extension* +
*Smcdeleg* +
*Smdbltrp* +
_Smdbltrp_ +
_Supervisor ISA_ +
*Svade Extension* +
*Svnapot Extension* +
@ -31,9 +31,10 @@ _Supervisor ISA_ +
*Svadu Extension* +
*Sstc* +
*Sscofpmf* +
*Ssdbltrp* +
_Ssdbltrp_ +
*Hypervisor ISA* +
_Shlcofideleg_
_Shlcofideleg_ +
*Svvptc*
|_1.13_ +
*1.0* +
@ -42,7 +43,7 @@ _Shlcofideleg_
*1.0* +
*1.0* +
*1.0* +
*1.0* +
_1.0_ +
_1.13_ +
*1.0* +
*1.0* +
@ -51,9 +52,10 @@ _1.13_ +
*1.0* +
*1.0* +
*1.0* +
_1.0_ +
*1.0* +
*1.0* +
_0.1_
_0.1_ +
*1.0*
|_Draft_ +
*Ratified* +
@ -73,7 +75,8 @@ _Draft_ +
*Ratified* +
_Draft_ +
*Ratified* +
_Draft_
_Draft_ +
*Ratified*
|===
The following changes have been made since version 1.12 of the Machine and
@ -98,6 +101,7 @@ implemented.
* Specified synchronization requirements when changing the PBMTE fields
in `menvcfg` and `henvcfg`.
* Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension.
* Relaxed behavior of some HINTs when MXLEN > XLEN.
Finally, the following clarifications and document improvments have been made
since the last document release:
@ -117,6 +121,8 @@ be set to a nonzero value but sometimes not.
* Clarified exception behavior of unimplemented or inaccessible CSRs.
* Clarified that Svpbmt allows implementations to override additional PMAs.
* Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.
* Clarified that timer and count-overflow interrupts' arrival in
interrupt-pending registers is not immediate.
[.big]*_Preface to Version 20211203_*

15
docs/riscv-isa/src/riscv-privileged.adoc
View file

@ -2,23 +2,19 @@ include::config.adoc[]
[[risc-v-isa]]
= The RISC-V Instruction Set Manual for {ohg-config}: Volume II: Privileged Architecture
include::../docs-resources/global-config.adoc[]
:description: Volume II - Privileged Architecture
:company: RISC-V.org
:revnumber: 20240612
:revnumber: 20240703
//:revremark: Pre-release version
//development: assume everything can change
//stable: assume everything could change
//frozen: of you implement this version you assume the risk that something might change because of the public review cycle but we expect little to no change.
//ratified: you can implement this and be assured nothing will change. if something needs to change due to an errata or enhancement, it will come out in a new extension. we do not revise extensions.
:url-riscv: http://riscv.org
:doctype: book
:colophon:
:pdf-theme: ../src/resources/themes/riscv-spec.yml
:pdf-fontsdir: ../src/resources/fonts/
:preface-title: Preamble
:appendix-caption: Appendix
:imagesdir: images
:title-logo-image: image:risc-v_logo.png[pdfwidth=3.25in,align=center]
:imagesdir: ../docs-resources/images
:title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center]
:page-background-image: image:draft.png[opacity=20%]
:title-page-background-image: image:ohg_logo.png[fit=none,pdfwidth=3.25in,position=top]
//:title-page-background-image: none
@ -27,7 +23,7 @@ include::config.adoc[]
:experimental:
:reproducible:
:imagesoutdir: images
:bibtex-file: ../src/resources/riscv-spec.bib
:bibtex-file: src/resources/riscv-spec.bib
:bibtex-order: alphabetical
:bibtex-style: apa
:bibtex-format: asciidoc
@ -61,6 +57,7 @@ endif::[]
:ne: &#8800;
:approx: &#8776;
:inf: &#8734;
:imagesdir: images
This document describes the RISC-V privileged architecture tailored for
OpenHW Group {ohg-config}.

17
docs/riscv-isa/src/riscv-unprivileged.adoc
View file

@ -2,19 +2,15 @@ include::config.adoc[]
[[risc-v-isa]]
= The RISC-V Instruction Set Manual for {ohg-config}: Volume I - Unprivileged Architecture
:description: Volume I - Unprivileged Architecture
:company: RISC-V.org
:revnumber: 20240612
include::../docs-resources/global-config.adoc[]
:description: Unprivileged Architecture
:revnumber: 20240703
//:revremark: Pre-release version
:url-riscv: http://riscv.org
:doctype: book
:colophon:
:pdf-theme: ../src/resources/themes/riscv-spec.yml
:pdf-fontsdir: ../src/resources/fonts/
:preface-title: Preamble
:appendix-caption: Appendix
:imagesdir: images
:title-logo-image: image:risc-v_logo.png[pdfwidth=3.25in,align=center]
:imagesdir: ../docs-resources/images
:title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center]
:page-background-image: image:draft.png[opacity=20%]
:title-page-background-image: image:ohg_logo.png[fit=none,pdfwidth=3.25in,position=top]
//:title-page-background-image: none
@ -24,7 +20,7 @@ include::config.adoc[]
:experimental:
:reproducible:
:imagesoutdir: images
:bibtex-file: ../src/resources/riscv-spec.bib
:bibtex-file: src/resources/riscv-spec.bib
:bibtex-order: alphabetical
:bibtex-style: apa
:bibtex-format: asciidoc
@ -58,6 +54,7 @@ endif::[]
:approx: &#8776;
:inf: &#8734;
:csrname: envcfg
:imagesdir: images
This document describes the RISC-V unprivileged architecture tailored for
OpenHW Group {ohg-config}.

127
docs/riscv-isa/src/supervisor.adoc
View file

@ -88,7 +88,8 @@ ifdef::archi-default,XLEN-32[]
{bits: 1, name: 'MXR'},
{bits: 3, name: 'WPRI'},
{bits: 1, name: 'SPELP'},
{bits: 7, name: 'WPRI'},
{bits: 1, name: 'SDT'},
{bits: 6, name: 'WPRI'},
{bits: 1, name: 'SD'},
], config:{lanes: 2, hspace:1024}}
....
@ -116,7 +117,8 @@ ifdef::archi-default,XLEN-64[]
{bits: 1, name: 'MXR'},
{bits: 3, name: 'WPRI'},
{bits: 1, name: 'SPELP'},
{bits: 8, name: 'WPRI'},
{bits: 1, name: 'SDT'},
{bits: 7, name: 'WPRI'},
{bits: 2, name: 'UXL[1:0]'},
{bits: 29, name: 'WPRI'},
{bits: 1, name: 'SD'},
@ -186,6 +188,22 @@ The effective XLEN in S-mode is termed _SXLEN_.
Its value is set to SXLEN=MXLEN.
endif::[]
ifdef::archi-default[]
Some HINT instructions are encoded as integer computational instructions that
overwrite their destination register with its current value, e.g.,
`c.addi x8, 0`.
When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the
destination register not all equal to bit XLEN-1, it is implementation-defined
whether bits SXLEN..XLEN of the destination register are unchanged or are
overwritten with copies of bit XLEN-1.
NOTE: This definition allows implementations to elide register writeback for
some HINTs, while allowing them to execute other HINTs in the same manner as
other integer computational instructions.
The implementation choice is observable only by S-mode with SXLEN > UXLEN; it
is invisible to U-mode.
endif::[]
[[sum]]
===== Memory Privilege in `sstatus` Register
@ -278,6 +296,70 @@ Access to the `SPELP` field, added by Zicfilp, accesses the homonymous
fields of `mstatus` when `V=0`, and the homonymous fields of `vsstatus`
when `V=1`.
[[supv-double-trap]]
===== Double Trap Control in `sstatus` Register
ifdef::archi-default,RVZssdbltrp-true[]
The S-mode-disable-trap (`SDT`) bit is a WARL field introduced by the Ssdbltrp
extension to address double trap (See <<machine-double-trap>>) at privilege
modes lower than M.
When the `SDT` bit is set to 1 by an explicit CSR write, the `SIE` (Supervisor
Interrupt Enable) bit is cleared to 0. This clearing occurs regardless of the
value written, if any, to the `SIE` bit by the same write. The `SIE` bit can
only be set to 1 by an explicit CSR write if the `SDT` bit is being set to 0 by
the same write or is already 0.
When a trap is to be taken into S-mode, if the `SDT` bit is currently 0,
it is then set to 1, and the trap is delivered as expected. However, if `SDT` is
already set to 1, then this is an _unexpected trap_. In the event of an
_unexpected trap_, a double-trap exception trap is delivered into M-mode. To
deliver this trap, the hart writes registers, except `mcause` and `mtval2`, with
the same information that the _unexpected trap_ would have written if it was
taken into M-mode. The `mtval2` register is then set to what would be otherwise
written into the `mcause` register by the _unexpected trap_. The `mcause`
register is set to 16, the double-trap exception code.
An `SRET` instruction sets the `SDT` bit to 0.
[NOTE]
====
After a trap handler has saved the state, such as `scause`, `sepc`,
and `stval`, needed for resuming from the trap and is reentrant, it
should clear the `SDT` bit.
Resetting the `SDT` by an `SRET` enables the trap handler to detect a double
trap that may occur during the tail phase, where it restores critical state
to return from a trap.
The consequence of this specification is that if a critical error condition was
caused by a guest page-fault, then the GPA will not be available in `mtval2`
when the double trap is delivered to M-mode. This condition arises if the
HS-mode invokes a hypervisor virtual-machine load or store instruction when
`SDT` is 1 and the instruction raises a guest page-fault. The use of such an
instruction in this phase of trap handling is not common. However, not recording
the GPA is considered benign because, if required, it can still be obtained
-- albeit with added effort -- through the process of walking the page tables.
For a double trap that originates in VS-mode, M-mode should redirect the exception
to HS-mode by copying the values of M-mode CSRs updated by the trap to HS-mode
CSRs and should use an `MRET` to resume execution at the address in `stvec`.
Supervisor Software Events (SSE), an extension to the SBI, provide a
mechanism for supervisor software to register and service system events
emanating from an SBI implementation, such as firmware or a hypervisor. In the
event of a double trap, HS-mode and M-mode can utilize the SSE mechanism to
invoke a critical-error handler in VS-mode or S/HS-mode, respectively.
Additionally, the implementation of an SSE protocol can be considered as an
optional measure to aid in the recovery from such critical errors.
====
endif::[]
ifndef::archi-default,RVZssdbltrp-true[]
[{ohg-config}] As Double Trap Control (Ssdbltrp extension) is not implemented,
SDT field is read-only 0.
endif::[]
==== Supervisor Trap Vector Base Address (`stvec`) Register
The `stvec` register is an SXLEN-bit read/write register that holds trap
@ -2511,31 +2593,34 @@ exceptions when A/D bits need be set, instead takes effect.
The Svade extension is also defined in <<translation>>.
[[sec:svvptc]]
== "Svvptc" Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0
== "Svvptc" Extension for Obviating Memory-Management Instructions after Marking PTEs Valid, Version 1.0
When the Svvptc extension is implemented, explicit stores that update the Valid
bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will
eventually become visible within a bounded timeframe to subsequent implicit
When the Svvptc extension is implemented, explicit stores by a hart that update
the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart
will eventually become visible within a bounded timeframe to subsequent implicit
accesses by that hart to such PTEs.
endif::[]
ifeval::[{note} == true]
[NOTE]
====
Typically, PTEs are marked as Valid by the operating system following a
page-fault exception or during system calls for memory mapping. In such cases,
the trap handler commonly employs an `SRET` instruction to return from the trap.
When Svvptc is implemented, the stores it executes to change the Valid bit
of the PTEs from 0 to 1 then become visible to implicit references to those PTEs
within a bounded timeframe. This visibility pertains to the instructions like
the one causing the page fault or those accessing new memory regions. A
memory-management fence can be used to force immediate visibility of these PTE
updates to all implicit references associated with instructions following the
memory-management fence. However, when Svvptc is implemented, visibility (in a
bounded amount of time) is guaranteed and use of a memory-management fence is
not required in these scenarios. While this approach might lead to an occasional
gratuitous page-fault, the performance benefit of omitting the memory-management
fence instructions outweighs the occasional cost of a gratuitous page fault.
Svvptc relieves an operating system from executing certain memory-management
instructions, such as `SFENCE.VMA` or `SINVAL.VMA`, which would normally be used
to synchronize the hart's address-translation caches when a memory-resident PTE
is changed from Invalid to Valid. Synchronizing the hart's address-translation
caches with other forms of updates to a memory-resident PTE, including when a
PTE is changed from Valid to Invalid, requires the use of suitable
memory-management instructions. Svvptc guarantees that a change to a PTE from
Invalid to Valid is made visible within a bounded time, thereby making the
execution of these memory-management instructions redundant. The performance
benefit of eliding these instructions outweighs the cost of an occasional
gratuitous additional page fault that may occur.
Depending on the microarchitecture, some possible ways to facilitate
implementation of Svvptc include: not having any address-translation caches, not
storing Invalid PTEs in the address-translation caches, automatically evicting
Invalid PTEs using a bounded timer, or making address-translation caches
coherent with store instructions that modify PTEs.
====
endif::[]
@ -2664,4 +2749,4 @@ contexts.
====
////
endif::[]
endif::[]