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Generate cv32a60x design document

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Fix cv32a65x design document

Update CVXIF design documentation

Remove DCACHE/ICACHE CSRs from spec, doc, and config files.

Remove cache description from cv32a60x

Update OBI interfaces specification for cv32a60x
This commit is contained in:
Jean-Roch Coulon 2025-04-04 23:55:00 +02:00
parent 33a66ee5b9
commit 0beb8314a0
38 changed files with 2758 additions and 298 deletions
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config/gen_from_riscv_config/Makefile Normal file
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# Copyright 2024 Thales DIS France SAS
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Original Author: Zbigniew CHAMSKI - Thales
# Name of the target to process
TARGET ?= cv32a65x
# Components, output formats and file/directory paths.
COMPONENTS = isa csr
FORMATS = rst adoc # no md anymore
SPEC_DIR = $(realpath ../riscv-config/$(TARGET)/generated)
SCRIPT = scripts/riscv_config_gen.py
GEN_DIR = $(TARGET)
# Input files
ISA_INPUT = $(SPEC_DIR)/isa_gen.yaml
CSR_INPUT = $(SPEC_DIR)/isa_gen.yaml
CUSTOM_INPUT = $(SPEC_DIR)/custom_gen.yaml
ifneq ($(wildcard $(CUSTOM_INPUT)),)
CUSTOM_ARG = -c $(CUSTOM_INPUT)
endif
# Templates
ISA_TEMPLATE = templates/isa_template.yaml
# Updaters can be disabled by setting BARE to non-empty value.
# Bare/updated output files are kept separate to enable comparisons.
ifeq ($(BARE),)
UPDATER_OPT = -m
ISA_UPDATER = updaters/$(TARGET)/isa_updater.yaml
CSR_UPDATER = updaters/$(TARGET)/csr_updater.yaml
ISA_OUTPUTS = $(patsubst %,$(GEN_DIR)/isa/isa.%,$(FORMATS))
CSR_OUTPUTS = $(patsubst %,$(GEN_DIR)/csr/csr.%,$(FORMATS))
else
# In 'bare' mode ($(BARE) not empty) do not apply updaters.
UPDATER_OPT =
ISA_UPDATER =
CSR_UPDATER =
ISA_OUTPUTS = $(patsubst %,$(GEN_DIR)/isa/isa_bare.%,$(FORMATS))
CSR_OUTPUTS = $(patsubst %,$(GEN_DIR)/csr/csr_bare.%,$(FORMATS))
endif
# Output files
ISA_ADOC = $(GEN_DIR)/isa/isa.adoc
ISA_MD = $(GEN_DIR)/isa/isa.md
ISA_RST = $(GEN_DIR)/isa/isa.rst
CSR_ADOC = $(GEN_DIR)/csr/csr.adoc
CSR_MD = $(GEN_DIR)/csr/csr.md
CSR_RST = $(GEN_DIR)/csr/csr.rst
OUTPUT_FILES = $(ISA_OUTPUTS) $(CSR_OUTPUTS)
# 'isa' and 'csr' Makefile targets are not actual files.
.PHONY: $(COMPONENTS)
# By default generate both ISA and CSR documentation in updated mode.
all: $(COMPONENTS)
adoc: $(ADOC_OUTPUTS)
isa: $(ISA_OUTPUTS)
csr: $(CSR_OUTPUTS)
%_bare.adoc: %.adoc
mv $^ $@
%_full.adoc: %.adoc
mv $^ $@
%_bare.md: %.md
mv $^ $@
%_full.md: %.md
mv $^ $@
%_bare.rst: %.rst
mv $^ $@
%_full.rst: %.rst
mv $^ $@
$(ISA_RST) $(ISA_MD) $(ISA_ADOC): $(ISA_INPUT) $(ISA_UPDATER) Makefile
pip3 install -r requirements.txt
-black scripts
python3 $(SCRIPT) -s $(ISA_INPUT) -i $(ISA_TEMPLATE) \
$(CUSTOM_ARG) \
-f $(subst .,,$(suffix $@)) \
$(UPDATER_OPT) $(ISA_UPDATER) -t $(TARGET)
$(CSR_RST) $(CSR_MD) $(CSR_ADOC): $(CSR_INPUT) $(CSR_UPDATER) Makefile
pip3 install -r requirements.txt
-black scripts
python3 $(SCRIPT) -s $(CSR_INPUT) \
$(CUSTOM_ARG) \
-f $(subst .,,$(suffix $@)) \
$(UPDATER_OPT) $(CSR_UPDATER) -t $(TARGET)
clean:
$(RM) $(OUTPUT_FILES)

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////
Copyright (c) 2024 OpenHW Group
Copyright (c) 2025 Thales DIS France SAS
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
Author: Abdessamii Oukalrazqou
////
=== csr
==== Conventions
In the subsequent sections, register fields are labeled with one of the following abbreviations:
* WPRI (Writes Preserve Values, Reads Ignore Values): read/write field reserved
for future use. For forward compatibility, implementations that do not
furnish these fields must make them read-only zero.
* WLRL (Write/Read Only Legal Values): read/write CSR field that specifies
behavior for only a subset of possible bit encodings, with other bit encodings
reserved.
* WARL (Write Any Values, Reads Legal Values): read/write CSR fields which are
only defined for a subset of bit encodings, but allow any value to be written
while guaranteeing to return a legal value whenever read.
* ROCST (Read-Only Constant): A special case of WARL field which admits only one
legal value, and therefore, behaves as a constant field that silently ignores
writes.
* ROVAR (Read-Only Variable): A special case of WARL field which can take
multiple legal values but cannot be modified by software and depends only on
the architectural state of the hart.
In particular, a register that is not internally divided
into multiple fields can be considered as containing a single field of XLEN bits.
This allows to clearly represent read-write registers holding a single legal value
(typically zero).
==== Register Summary
|===
|Address | Register Name | Privilege | Description
|0x300| `<<_MSTATUS,MSTATUS>>`|MRW|The mstatus register keeps track of and controls the hart's current operating state.
|0x301| `<<_MISA,MISA>>`|MRW|misa is a read-write register reporting the ISA supported by the hart.
|0x304| `<<_MIE,MIE>>`|MRW|The mie register is an MXLEN-bit read/write register containing interrupt enable bits.
|0x305| `<<_MTVEC,MTVEC>>`|MRW|MXLEN-bit read/write register that holds trap vector configuration.
|0x310| `<<_MSTATUSH,MSTATUSH>>`|MRW|The mstatush register keeps track of and controls the hart’s current operating state.
|0x323-0x33f| `<<_MHPMEVENT3-31,MHPMEVENT[3-31]>>`|MRW|The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.
|0x340| `<<_MSCRATCH,MSCRATCH>>`|MRW|The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.
|0x341| `<<_MEPC,MEPC>>`|MRW|The mepc is a warl register that must be able to hold all valid physical and virtual addresses.
|0x342| `<<_MCAUSE,MCAUSE>>`|MRW|The mcause register stores the information regarding the trap.
|0x343| `<<_MTVAL,MTVAL>>`|MRW|The mtval is a warl register that holds the address of the instruction which caused the exception.
|0x344| `<<_MIP,MIP>>`|MRW|The mip register is an MXLEN-bit read/write register containing information on pending interrupts.
|0x3a0-0x3af| `<<_PMPCFG0-15,PMPCFG[0-15]>>`|MRW|PMP configuration register
|0x3b0-0x3ef| `<<_PMPADDR0-63,PMPADDR[0-63]>>`|MRW|Physical memory protection address register
|0xb00| `<<_MCYCLE,MCYCLE>>`|MRW|Counts the number of clock cycles executed from an arbitrary point in time.
|0xb02| `<<_MINSTRET,MINSTRET>>`|MRW|Counts the number of instructions completed from an arbitrary point in time.
|0xb03-0xb1f| `<<_MHPMCOUNTER3-31,MHPMCOUNTER[3-31]>>`|MRW|The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.
|0xb80| `<<_MCYCLEH,MCYCLEH>>`|MRW|upper 32 bits of mcycle
|0xb82| `<<_MINSTRETH,MINSTRETH>>`|MRW|Upper 32 bits of minstret.
|0xb83-0xb9f| `<<_MHPMCOUNTER3-31H,MHPMCOUNTER[3-31]H>>`|MRW|The mhpmcounterh returns the upper half word in RV32I systems.
|0xf11| `<<_MVENDORID,MVENDORID>>`|MRO|32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.
|0xf12| `<<_MARCHID,MARCHID>>`|MRO|MXLEN-bit read-only register encoding the base microarchitecture of the hart.
|0xf13| `<<_MIMPID,MIMPID>>`|MRO|Provides a unique encoding of the version of the processor implementation.
|0xf14| `<<_MHARTID,MHARTID>>`|MRO|MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.
|0xf15| `<<_MCONFIGPTR,MCONFIGPTR>>`|MRO|MXLEN-bit read-only register that holds the physical address of a configuration data structure.
|===
==== Register Description
[[_MSTATUS]]
===== MSTATUS
Address:: 0x300
Reset Value:: 0x00001800
Privilege:: MRW
Description:: The mstatus register keeps track of and controls the hart's current operating state.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| 0 | UIE | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts.
| 1 | SIE | 0x0 | ROCST | 0x0 | Stores the state of the supervisor mode interrupts.
| 2 | RESERVED_2 | 0x0 | WPRI | | _Reserved_
| 3 | MIE | 0x0 | WLRL | 0x0 - 0x1 | Stores the state of the machine mode interrupts.
| 4 | UPIE | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts prior to the trap.
| 5 | SPIE | 0x0 | ROCST | 0x0 | Stores the state of the supervisor mode interrupts prior to the trap.
| 6 | UBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for user mode
| 7 | MPIE | 0x0 | WLRL | 0x0 - 0x1 | Stores the state of the machine mode interrupts prior to the trap.
| 8 | SPP | 0x0 | ROCST | 0x0 | Stores the previous priority mode for supervisor.
| [10:9] | RESERVED_9 | 0x0 | WPRI | | _Reserved_
| [12:11] | MPP | 0x3 | WARL | 0x3 | Stores the previous priority mode for machine.
| [14:13] | FS | 0x0 | ROCST | 0x0 | Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers.
| [16:15] | XS | 0x0 | ROCST | 0x0 | Encodes the status of additional user-mode extensions and associated state.
| 17 | MPRV | 0x0 | ROCST | 0x0 | Modifies the privilege level at which loads and stores execute in all privilege modes.
| 18 | SUM | 0x0 | ROCST | 0x0 | Modifies the privilege with which S-mode loads and stores access virtual memory.
| 19 | MXR | 0x0 | ROCST | 0x0 | Modifies the privilege with which loads access virtual memory.
| 20 | TVM | 0x0 | ROCST | 0x0 | Supports intercepting supervisor virtual-memory management operations.
| 21 | TW | 0x0 | ROCST | 0x0 | Supports intercepting the WFI instruction.
| 22 | TSR | 0x0 | ROCST | 0x0 | Supports intercepting the supervisor exception return instruction.
| 23 | SPELP | 0x0 | ROCST | 0x0 | Supervisor mode previous expected-landing-pad (ELP) state.
| [30:24] | RESERVED_24 | 0x0 | WPRI | | _Reserved_
| 31 | SD | 0x0 | ROCST | 0x0 | Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state.
|===
[[_MISA]]
===== MISA
Address:: 0x301
Reset Value:: 0x40001106
Privilege:: MRW
Description:: misa is a read-write register reporting the ISA supported by the hart.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [25:0] | EXTENSIONS | 0x1106 | ROCST | 0x1106 | Encodes the presence of the standard extensions, with a single bit per letter of the alphabet.
| [29:26] | RESERVED_26 | 0x0 | WPRI | | _Reserved_
| [31:30] | MXL | 0x1 | WARL | 0x1 | Encodes the native base integer ISA width.
|===
[[_MIE]]
===== MIE
Address:: 0x304
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mie register is an MXLEN-bit read/write register containing interrupt enable bits.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| 0 | USIE | 0x0 | ROCST | 0x0 | User Software Interrupt enable.
| 1 | SSIE | 0x0 | ROCST | 0x0 | Supervisor Software Interrupt enable.
| 2 | VSSIE | 0x0 | ROCST | 0x0 | VS-level Software Interrupt enable.
| 3 | MSIE | 0x0 | ROCST | 0x0 | Machine Software Interrupt enable.
| 4 | UTIE | 0x0 | ROCST | 0x0 | User Timer Interrupt enable.
| 5 | STIE | 0x0 | ROCST | 0x0 | Supervisor Timer Interrupt enable.
| 6 | VSTIE | 0x0 | ROCST | 0x0 | VS-level Timer Interrupt enable.
| 7 | MTIE | 0x0 | WLRL | 0x0 - 0x1 | Machine Timer Interrupt enable.
| 8 | UEIE | 0x0 | ROCST | 0x0 | User External Interrupt enable.
| 9 | SEIE | 0x0 | ROCST | 0x0 | Supervisor External Interrupt enable.
| 10 | VSEIE | 0x0 | ROCST | 0x0 | VS-level External Interrupt enable.
| 11 | MEIE | 0x0 | WLRL | 0x0 - 0x1 | Machine External Interrupt enable.
| 12 | SGEIE | 0x0 | ROCST | 0x0 | HS-level External Interrupt enable.
| [31:13] | RESERVED_13 | 0x0 | WPRI | | _Reserved_
|===
[[_MTVEC]]
===== MTVEC
Address:: 0x305
Reset Value:: 0x80010000
Privilege:: MRW
Description:: MXLEN-bit read/write register that holds trap vector configuration.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [1:0] | MODE | 0x0 | WARL | 0x0 | Vector mode.
| [31:2] | BASE | 0x20004000 | WARL | 0x00000000 - 0x3FFFFFFF | Vector base address.
|===
[[_MSTATUSH]]
===== MSTATUSH
Address:: 0x310
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mstatush register keeps track of and controls the hart’s current operating state.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [3:0] | RESERVED_0 | 0x0 | WPRI | | _Reserved_
| 4 | SBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for supervisor mode
| 5 | MBE | 0x0 | ROCST | 0x0 | control the endianness of memory accesses other than instruction fetches for machine mode
| 6 | GVA | 0x0 | ROCST | 0x0 | Stores the state of the supervisor mode interrupts.
| 7 | MPV | 0x0 | ROCST | 0x0 | Stores the state of the user mode interrupts.
| 8 | RESERVED_8 | 0x0 | WPRI | | _Reserved_
| 9 | MPELP | 0x0 | ROCST | 0x0 | Machine mode previous expected-landing-pad (ELP) state.
| [31:10] | RESERVED_10 | 0x0 | WPRI | | _Reserved_
|===
[[_MHPMEVENT3-31]]
===== MHPMEVENT[3-31]
Address:: 0x323-0x33f
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MHPMEVENT[I] | 0x00000000 | ROCST | 0x0 | The mhpmevent is a MXLEN-bit event register which controls mhpmcounter3.
|===
[[_MSCRATCH]]
===== MSCRATCH
Address:: 0x340
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MSCRATCH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.
|===
[[_MEPC]]
===== MEPC
Address:: 0x341
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mepc is a warl register that must be able to hold all valid physical and virtual addresses.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MEPC | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | The mepc is a warl register that must be able to hold all valid physical and virtual addresses.
|===
[[_MCAUSE]]
===== MCAUSE
Address:: 0x342
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mcause register stores the information regarding the trap.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [30:0] | EXCEPTION_CODE | 0x0 | WLRL | 0x0 - 0x8, 0xb | Encodes the exception code.
| 31 | INTERRUPT | 0x0 | WLRL | 0x0 - 0x1 | Indicates whether the trap was due to an interrupt.
|===
[[_MTVAL]]
===== MTVAL
Address:: 0x343
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mtval is a warl register that holds the address of the instruction which caused the exception.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MTVAL | 0x00000000 | ROCST | 0x0 | The mtval is a warl register that holds the address of the instruction which caused the exception.
|===
[[_MIP]]
===== MIP
Address:: 0x344
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mip register is an MXLEN-bit read/write register containing information on pending interrupts.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| 0 | USIP | 0x0 | ROCST | 0x0 | User Software Interrupt Pending.
| 1 | SSIP | 0x0 | ROCST | 0x0 | Supervisor Software Interrupt Pending.
| 2 | VSSIP | 0x0 | ROCST | 0x0 | VS-level Software Interrupt Pending.
| 3 | MSIP | 0x0 | ROCST | 0x0 | Machine Software Interrupt Pending.
| 4 | UTIP | 0x0 | ROCST | 0x0 | User Timer Interrupt Pending.
| 5 | STIP | 0x0 | ROCST | 0x0 | Supervisor Timer Interrupt Pending.
| 6 | VSTIP | 0x0 | ROCST | 0x0 | VS-level Timer Interrupt Pending.
| 7 | MTIP | 0x0 | ROVAR | 0x0 - 0x1 | Machine Timer Interrupt Pending.
| 8 | UEIP | 0x0 | ROCST | 0x0 | User External Interrupt Pending.
| 9 | SEIP | 0x0 | ROCST | 0x0 | Supervisor External Interrupt Pending.
| 10 | VSEIP | 0x0 | ROCST | 0x0 | VS-level External Interrupt Pending.
| 11 | MEIP | 0x0 | ROVAR | 0x0 - 0x1 | Machine External Interrupt Pending.
| 12 | SGEIP | 0x0 | ROCST | 0x0 | HS-level External Interrupt Pending.
| [31:13] | RESERVED_13 | 0x0 | WPRI | | _Reserved_
|===
[[_PMPCFG0-15]]
===== PMPCFG[0-15]
Address:: 0x3a0-0x3af
Reset Value:: 0x00000000
Privilege:: MRW
Description:: PMP configuration register
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [7:0] | PMP[I*4 +0]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits
| [15:8] | PMP[I*4 +1]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits
| [23:16] | PMP[I*4 +2]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits
| [31:24] | PMP[I*4 +3]CFG | 0x0 | ROCST | 0x0 | pmp configuration bits
|===
[[_PMPADDR0-63]]
===== PMPADDR[0-63]
Address:: 0x3b0-0x3ef
Reset Value:: 0x00000000
Privilege:: MRW
Description:: Physical memory protection address register
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | PMPADDR[I] | 0x00000000 | ROCST | 0x0 | Physical memory protection address register
|===
[[_MCYCLE]]
===== MCYCLE
Address:: 0xb00
Reset Value:: 0x00000000
Privilege:: MRW
Description:: Counts the number of clock cycles executed from an arbitrary point in time.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MCYCLE | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Counts the number of clock cycles executed from an arbitrary point in time.
|===
[[_MINSTRET]]
===== MINSTRET
Address:: 0xb02
Reset Value:: 0x00000000
Privilege:: MRW
Description:: Counts the number of instructions completed from an arbitrary point in time.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MINSTRET | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Counts the number of instructions completed from an arbitrary point in time.
|===
[[_MHPMCOUNTER3-31]]
===== MHPMCOUNTER[3-31]
Address:: 0xb03-0xb1f
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MHPMCOUNTER[I] | 0x00000000 | ROCST | 0x0 | The mhpmcounter is a 64-bit counter. Returns lower 32 bits in RV32I mode.
|===
[[_MCYCLEH]]
===== MCYCLEH
Address:: 0xb80
Reset Value:: 0x00000000
Privilege:: MRW
Description:: upper 32 bits of mcycle
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MCYCLEH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | upper 32 bits of mcycle
|===
[[_MINSTRETH]]
===== MINSTRETH
Address:: 0xb82
Reset Value:: 0x00000000
Privilege:: MRW
Description:: Upper 32 bits of minstret.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MINSTRETH | 0x00000000 | WARL | 0x00000000 - 0xFFFFFFFF | Upper 32 bits of minstret.
|===
[[_MHPMCOUNTER3-31H]]
===== MHPMCOUNTER[3-31]H
Address:: 0xb83-0xb9f
Reset Value:: 0x00000000
Privilege:: MRW
Description:: The mhpmcounterh returns the upper half word in RV32I systems.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MHPMCOUNTER[I]H | 0x00000000 | ROCST | 0x0 | The mhpmcounterh returns the upper half word in RV32I systems.
|===
[[_MVENDORID]]
===== MVENDORID
Address:: 0xf11
Reset Value:: 0x00000602
Privilege:: MRO
Description:: 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MVENDORID | 0x00000602 | ROCST | 0x602 | 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.
|===
[[_MARCHID]]
===== MARCHID
Address:: 0xf12
Reset Value:: 0x00000003
Privilege:: MRO
Description:: MXLEN-bit read-only register encoding the base microarchitecture of the hart.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MARCHID | 0x00000003 | ROCST | 0x3 | MXLEN-bit read-only register encoding the base microarchitecture of the hart.
|===
[[_MIMPID]]
===== MIMPID
Address:: 0xf13
Reset Value:: 0x00000000
Privilege:: MRO
Description:: Provides a unique encoding of the version of the processor implementation.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MIMPID | 0x00000000 | ROCST | 0x0 | Provides a unique encoding of the version of the processor implementation.
|===
[[_MHARTID]]
===== MHARTID
Address:: 0xf14
Reset Value:: 0x00000000
Privilege:: MRO
Description:: MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MHARTID | 0x00000000 | ROCST | 0x0 | MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.
|===
[[_MCONFIGPTR]]
===== MCONFIGPTR
Address:: 0xf15
Reset Value:: 0x00000000
Privilege:: MRO
Description:: MXLEN-bit read-only register that holds the physical address of a configuration data structure.
|===
| Bits | Field Name | Reset Value | Type | Legal Values | Description
| [31:0] | MCONFIGPTR | 0x00000000 | ROCST | 0x0 | MXLEN-bit read-only register that holds the physical address of a configuration data structure.
|===

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////
Copyright (c) 2025 Thales DIS France SAS
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
Author: Abdessamii Oukalrazqou
////
=== isa
==== Instructions
|===
|Subset Name | Name | Description
|I | RV32I Base Integer Instructions | the base integer instruction set, also known as the 'RV32I' or 'RV64I' instruction set , depending on the address space size, provides the core functionality required for general-purpose computing .it includes instructions for arithmetic, logical, and control operations, as well as memory accessand manipulation
|M | RV32M Multiplication and Division Instructions | the standard integer multiplication and division instruction extension, which is named “M” and contains instructions that multiply or divide values held in two integer registers.
|C | RV32C Compressed Instructions | RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V instructions when: the immediate or address offset is small; one of the registers is the zero register (x0), the ABI link register (x1), or the ABI stack pointer (x2); the destination register and the first source register are identical; the registers used are the 8 most popular ones.The C extension is compatible with all other standard instruction extensions. The C extension allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able to start on any 16-bit boundary. With the addition of the C extension, JAL and JALR instructions will no longer raise an instruction misaligned exception
|Zicsr | RV32Zicsr Control and Status Register Instructions | All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field.
|Zcb | RV32Zcb Code Size Reduction Instructions | Zcb belongs to the group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of the Standard C extension adding more 16-bit instructions to the ISA. Zcb includes the 16-bit version of additional Integer (I), Multiply (M), and Bit-Manipulation (Zbb) Instructions. All the Zcb instructions require at least standard C extension support as a prerequisite, along with M and Zbb extensions for the 16-bit version of the respective instructions.
|Zba | RVZba Address generation instructions | The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address. The shift and add instructions do a left shift of 1, 2, or 3 because these are commonly found in real-world code and because they can be implemented with a minimal amount of additional hardware beyond that of the simple adder. This avoids lengthening the critical path in implementations. While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction (from the base ISA) can be used to perform similar shifts for indexing into arrays of wider elements. The slli.uw added in this extension can be used when the index is to be interpreted as an unsigned word.
|Zbb | RVZbb Basic bit-manipulation | The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction. While the instructions are intended to have general use, some instructions are more useful in some domains than others. Hence, several smaller bitmanip extensions are provided. Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name.
|Zbc | RVZbc Carry-less multiplication | Carry-less multiplication is the multiplication in the polynomial ring over GF(2).clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product.clmulr produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product.
|Zbs | RVZbs Single bit Instructions | The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index.
|Xcvxif | Xcvxif | No info found yet for extension Xcvxif
|===
==== RV32I Base Integer Instructions
|===
| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name
| ADDI | addi rd, rs1, imm[11:0] | x[rd] = x[rs1] + sext(imm[11:0]) | NONE | NONE | add sign-extended 12-bit immediate to register rs1, and store the result in register rd. | Integer_Register_Immediate_Operations
| ANDI | andi rd, rs1, imm[11:0] | x[rd] = x[rs1] & sext(imm[11:0]) | NONE | NONE | perform bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd. | Integer_Register_Immediate_Operations
| ORI | ori rd, rs1, imm[11:0] | x[rd] = x[rs1] \| sext(imm[11:0]) | NONE | NONE | perform bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. | Integer_Register_Immediate_Operations
| XORI | xori rd, rs1, imm[11:0] | x[rd] = x[rs1] ^ sext(imm[11:0]) | NONE | NONE | perform bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. | Integer_Register_Immediate_Operations
| SLTI | slti rd, rs1, imm[11:0] | if (x[rs1] < sext(imm[11:0])) x[rd] = 1 else x[rd] = 0 | NONE | NONE | set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as signed numbers, else 0 is written to rd. | Integer_Register_Immediate_Operations
| SLTIU | sltiu rd, rs1, imm[11:0] | if (x[rs1] <u sext(imm[11:0])) x[rd] = 1 else x[rd] = 0 | NONE | NONE | set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as unsigned numbers, else 0 is written to rd." | Integer_Register_Immediate_Operations
| SLLI | slli rd, rs1, imm[4:0] | x[rd] = x[rs1] << imm[4:0] | NONE | NONE | logical left shift (zeros are shifted into the lower bits). | Integer_Register_Immediate_Operations
| SRLI | srli rd, rs1, imm[4:0] | x[rd] = x[rs1] >> imm[4:0] | NONE | NONE | logical right shift (zeros are shifted into the upper bits). | Integer_Register_Immediate_Operations
| SRAI | srai rd, rs1, imm[4:0] | x[rd] = x[rs1] >>s imm[4:0] | NONE | NONE | arithmetic right shift (the original sign bit is copied into the vacated upper bits). | Integer_Register_Immediate_Operations
| LUI | lui rd, imm[19:0] | x[rd] = sext(imm[31:12] << 12) | NONE | NONE | place the immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros. | Integer_Register_Immediate_Operations
| AUIPC | auipc rd, imm[19:0] | x[rd] = pc + sext(immediate[31:12] << 12) | NONE | NONE | form a 32-bit offset from the 20-bit immediate, filling in the lowest 12 bits with zeros, adds this offset to the pc, then place the result in register rd. | Integer_Register_Immediate_Operations
| ADD | add rd, rs1, rs2 | x[rd] = x[rs1] + x[rs2] | NONE | NONE | add rs2 to register rs1, and store the result in register rd. | Integer_Register_Register_Operations
| SUB | sub rd, rs1, rs2 | x[rd] = x[rs1] - x[rs2] | NONE | NONE | subtract rs2 from register rs1, and store the result in register rd. | Integer_Register_Register_Operations
| AND | and rd, rs1, rs2 | x[rd] = x[rs1] & x[rs2] | NONE | NONE | perform bitwise AND on register rs1 and rs2 and place the result in rd. | Integer_Register_Register_Operations
| OR | or rd, rs1, rs2 | x[rd] = x[rs1] \| x[rs2] | NONE | NONE | perform bitwise OR on register rs1 and rs2 and place the result in rd. | Integer_Register_Register_Operations
| XOR | xor rd, rs1, rs2 | x[rd] = x[rs1] ^ x[rs2] | NONE | NONE | perform bitwise XOR on register rs1 and rs2 and place the result in rd. | Integer_Register_Register_Operations
| SLT | slt rd, rs1, rs2 | if (x[rs1] < x[rs2]) x[rd] = 1 else x[rd] = 0 | NONE | NONE | set register rd to 1 if register rs1 is less than rs2 when both are treated as signed numbers, else 0 is written to rd. | Integer_Register_Register_Operations
| SLTU | sltu rd, rs1, rs2 | if (x[rs1] <u x[rs2]) x[rd] = 1 else x[rd] = 0 | NONE | NONE | set register rd to 1 if register rs1 is less than rs2 when both are treated as unsigned numbers, else 0 is written to rd. | Integer_Register_Register_Operations
| SLL | sll rd, rs1, rs2 | x[rd] = x[rs1] << x[rs2] | NONE | NONE | logical left shift (zeros are shifted into the lower bits). | Integer_Register_Register_Operations
| SRL | srl rd, rs1, rs2 | x[rd] = x[rs1] >> x[rs2] | NONE | NONE | logical right shift (zeros are shifted into the upper bits). | Integer_Register_Register_Operations
| SRA | sra rd, rs1, rs2 | x[rd] = x[rs1] >>s x[rs2] | NONE | NONE | arithmetic right shift (the original sign bit is copied into the vacated upper bits). | Integer_Register_Register_Operations
| JAL | jal rd, imm[20:1] | x[rd] = pc+4; pc += sext(imm[20:1]) | NONE | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | offset is sign-extended and added to the pc to form the jump target address (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd. | Control_Transfer_Operations-Unconditional_Jumps
| JALR | jalr rd, rs1, imm[11:0] | t = pc+4; pc = (x[rs1]+sext(imm[11:0]))&∼1 ; x[rd] = t | NONE | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | target address is obtained by adding the 12-bit signed immediate to the register rs1 (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd. | Control_Transfer_Operations-Unconditional_Jumps
| BEQ | beq rs1, rs2, imm[12:1] | if (x[rs1] == x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are equal. | Control_Transfer_Operations-Conditional_Branches
| BNE | bne rs1, rs2, imm[12:1] | if (x[rs1] != x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are not equal. | Control_Transfer_Operations-Conditional_Branches
| BLT | blt rs1, rs2, imm[12:1] | if (x[rs1] < x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using signed comparison). | Control_Transfer_Operations-Conditional_Branches
| BLTU | bltu rs1, rs2, imm[12:1] | if (x[rs1] <u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using unsigned comparison). | Control_Transfer_Operations-Conditional_Branches
| BGE | bge rs1, rs2, imm[12:1] | if (x[rs1] >= x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using signed comparison). | Control_Transfer_Operations-Conditional_Branches
| BGEU | bgeu rs1, rs2, imm[12:1] | if (x[rs1] >=u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4 | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using unsigned comparison). | Control_Transfer_Operations-Conditional_Branches
| LB | lb rd, imm(rs1) | x[rd] = sext(M[x[rs1] + sext(imm[11:0])][7:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded. | loads a 8-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions
| LH | lh rd, imm(rs1) | x[rd] = sext(M[x[rs1] + sext(imm[11:0])][15:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary). | loads a 16-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions
| LW | lw rd, imm(rs1) | x[rd] = sext(M[x[rs1] + sext(imm[11:0])][31:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (4-byte boundary). | loads a 32-bit value from memory, then storing in rd (rd is calculated using signed arithmetic). The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions
| LBU | lbu rd, imm(rs1) | x[rd] = zext(M[x[rs1] + sext(imm[11:0])][7:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded. | loads a 8-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions
| LHU | lhu rd, imm(rs1) | x[rd] = zext(M[x[rs1] + sext(imm[11:0])][15:0]) | NONE | loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary). | loads a 16-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions
| SB | sb rs2, imm(rs1) | M[x[rs1] + sext(imm[11:0])][7:0] = x[rs2][7:0] | NONE | NONE | stores a 8-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions
| SH | sh rs2, imm(rs1) | M[x[rs1] + sext(imm[11:0])][15:0] = x[rs2][15:0] | NONE | an exception is raised if the memory address isn't aligned (2-byte boundary). | stores a 16-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions
| SW | sw rs2, imm(rs1) | M[x[rs1] + sext(imm[11:0])][31:0] = x[rs2][31:0] | NONE | an exception is raised if the memory address isn't aligned (4-byte boundary). | stores a 32-bit value from register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset. | Load_and_Store_Instructions
| FENCE | fence pre, succ | No operation (nop) | NONE | NONE | order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE, as the core support 1 hart, the fence instruction has no effect so we can considerate it as a nop instruction. | Memory_Ordering
| ECALL | ecall | RaiseException(EnvironmentCall) | NONE | Raise an Environment Call exception. | make a request to the supporting execution environment, which is usually an operating system. The ABI for the system will define how parameters for the environment request are passed, but usually these will be in defined locations in the integer register file. | Environment_Call_and_Breakpoints
| EBREAK | ebreak | x[8 + rd'] = sext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Environment_Call_and_Breakpoints
|===
==== RV32M Multiplication and Division Instructions
|===
| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name
| MUL | mul rd, rs1, rs2 | x[rd] = x[rs1] * x[rs2] | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rs1 and rs2 treated as signed numbers). | Multiplication Operations
| MULH | mulh rd, rs1, rs2 | x[rd] = (x[rs1] s*s x[rs2]) >>s 32 | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as signed numbers). | Multiplication Operations
| MULHU | mulhu rd, rs1, rs2 | x[rd] = (x[rs1] u*u x[rs2]) >>u 32 | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as unsigned numbers). | Multiplication Operations
| MULHSU | mulhsu rd, rs1, rs2 | x[rd] = (x[rs1] s*u x[rs2]) >>s 32 | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (rs1 treated as signed number, rs2 treated as unsigned number). | Multiplication Operations
| DIV | div rd, rs1, rs2 | x[rd] = x[rs1] /s x[rs2] | NONE | NONE | perform signed integer division of 32 bits by 32 bits (rounding towards zero). | Division Operations
| DIVU | divu rd, rs1, rs2 | x[rd] = x[rs1] /u x[rs2] | NONE | NONE | perform unsigned integer division of 32 bits by 32 bits (rounding towards zero). | Division Operations
| REM | rem rd, rs1, rs2 | x[rd] = x[rs1] %s x[rs2] | NONE | NONE | provide the remainder of the corresponding division operation DIV (the sign of rd equals the sign of rs1). | Division Operations
| REMU | rem rd, rs1, rs2 | x[rd] = x[rs1] %u x[rs2] | NONE | NONE | provide the remainder of the corresponding division operation DIVU. | Division Operations
|===
==== RV32C Compressed Instructions
|===
| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name
| C.LI | c.li rd, imm[5:0] | x[rd] = sext(imm[5:0]) | rd = x0 | NONE | loads the sign-extended 6-bit immediate, imm, into register rd. | Integer Computational Instructions
| C.LUI | c.lui rd, nzimm[17:12] | x[rd] = sext(nzimm[17:12] << 12) | rd = x0 & rd = x2 & nzimm = 0 | NONE | loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. | Integer Computational Instructions
| C.ADDI | c.addi rd, nzimm[5:0] | x[rd] = x[rd] + sext(nzimm[5:0]) | rd = x0 & nzimm = 0 | NONE | adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd. | Integer Computational Instructions
| C.ADDI16SP | c.addi16sp nzimm[9:4] | x[2] = x[2] + sext(nzimm[9:4]) | rd != x2 & nzimm = 0 | NONE | adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. C.ADDI16SP shares the opcode with C.LUI, but has a destination field of x2. | Integer Computational Instructions
| C.ADDI4SPN | c.addi4spn rd', nzimm[9:2] | x[8 + rd'] = x[2] + zext(nzimm[9:2]) | nzimm = 0 | NONE | adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables. | Integer Computational Instructions
| C.SLLI | c.slli rd, uimm[5:0] | x[rd] = x[rd] << uimm[5:0] | rd = x0 & uimm[5] = 0 | NONE | performs a logical left shift (zeros are shifted into the lower bits). | Integer Computational Instructions
| C.SRLI | c.srli rd', uimm[5:0] | x[8 + rd'] = x[8 + rd'] >> uimm[5:0] | uimm[5] = 0 | NONE | performs a logical right shift (zeros are shifted into the upper bits). | Integer Computational Instructions
| C.SRAI | c.srai rd', uimm[5:0] | x[8 + rd'] = x[8 + rd'] >>s uimm[5:0] | uimm[5] = 0 | NONE | performs an arithmetic right shift (sign bits are shifted into the upper bits). | Integer Computational Instructions
| C.ANDI | c.andi rd', imm[5:0] | x[8 + rd'] = x[8 + rd'] & sext(imm[5:0]) | NONE | NONE | computes the bitwise AND of the value in register rd', and the sign-extended 6-bit immediate, then writes the result to rd'. | Integer Computational Instructions
| C.ADD | c.add rd, rs2 | x[rd] = x[rd] + x[rs2] | rd = x0 & rs2 = x0 | NONE | adds the values in registers rd and rs2 and writes the result to register rd. | Integer Computational Instructions
| C.MV | c.mv rd, rs2 | x[rd] = x[rs2] | rd = x0 & rs2 = x0 | NONE | copies the value in register rs2 into register rd. | Integer Computational Instructions
| C.AND | c.and rd', rs2' | x[8 + rd'] = x[8 + rd'] & x[8 + rs2'] | NONE | NONE | computes the bitwise AND of of the value in register rd', and register rs2', then writes the result to rd'. | Integer Computational Instructions
| C.OR | c.or rd', rs2' | x[8 + rd'] = x[8 + rd'] \| x[8 + rs2'] | NONE | NONE | computes the bitwise OR of of the value in register rd', and register rs2', then writes the result to rd'. | Integer Computational Instructions
| C.XOR | c.and rd', rs2' | x[8 + rd'] = x[8 + rd'] ^ x[8 + rs2'] | NONE | NONE | computes the bitwise XOR of of the value in register rd', and register rs2', then writes the result to rd'. | Integer Computational Instructions
| C.SUB | c.sub rd', rs2' | x[8 + rd'] = x[8 + rd'] - x[8 + rs2'] | NONE | NONE | subtracts the value in registers rs2' from value in rd' and writes the result to register rd'. | Integer Computational Instructions
| C.EBREAK | c.ebreak | RaiseException(Breakpoint) | NONE | Raise a Breakpoint exception. | cause control to be transferred back to the debugging environment. | Integer Computational Instructions
| C.J | c.j imm[11:1] | pc += sext(imm[11:1]) | NONE | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. | Control Transfer Instructions
| C.JAL | c.jal imm[11:1] | x[1] = pc+2; pc += sext(imm[11:1]) | NONE | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. | Control Transfer Instructions
| C.JR | c.jr rs1 | pc = x[rs1] | rs1 = x0 | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | performs an unconditional control transfer to the address in register rs1. | Control Transfer Instructions
| C.JALR | c.jalr rs1 | t = pc+2; pc = x[rs1]; x[1] = t | rs1 = x0 | jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception. | performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. | Control Transfer Instructions
| C.BEQZ | c.beqz rs1', imm[8:1] | if (x[8+rs1'] == 0) pc += sext(imm[8:1]) | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' is zero. | Control Transfer Instructions
| C.BNEZ | c.bnez rs1', imm[8:1] | if (x[8+rs1'] != 0) pc += sext(imm[8:1]) | NONE | no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions. | performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' isn't zero. | Control Transfer Instructions
| C.LWSP | c.lwsp rd, uimm(x2) | x[rd] = M[x[2] + zext(uimm[7:2])][31:0] | rd = x0 | loads with a destination of x0 must still raise any exceptions, also an exception if the memory address isn't aligned (4-byte boundary). | loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. | Load and Store Instructions
| C.SWSP | c.swsp rd, uimm(x2) | M[x[2] + zext(uimm[7:2])][31:0] = x[rs2] | NONE | an exception raised if the memory address isn't aligned (4-byte boundary). | stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2. | Load and Store Instructions
| C.LW | c.lw rd', uimm(rs1') | x[8+rd'] = M[x[8+rs1'] + zext(uimm[6:2])][31:0]) | NONE | an exception raised if the memory address isn't aligned (4-byte boundary). | loads a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. | Load and Store Instructions
| C.SW | c.sw rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[6:2])][31:0] = x[8+rs2'] | NONE | an exception raised if the memory address isn't aligned (4-byte boundary). | stores a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'. | Load and Store Instructions
|===
==== RV32Zicsr Control and Status Register Instructions
|===
| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name
| CSRRW | csrrw rd, csr, rs1 | t = CSRs[csr]; CSRs[csr] = x[rs1]; x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. | Control and Status Register Operations
| CSRRS | csrrs rd, csr, rs1 | t = CSRs[csr]; CSRs[csr] = t \| x[rs1]; x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. | Control and Status Register Operations
| CSRRC | csrrc rd, csr, rs1 | t = CSRs[csr]; CSRs[csr] = t & ∼x[rs1]; x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. | Control and Status Register Operations
| CSRRWI | csrrwi rd, csr, uimm[4:0] | x[rd] = CSRs[csr]; CSRs[csr] = zext(uimm[4:0]) | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd. The zero-extends immediate is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read. | Control and Status Register Operations
| CSRRSI | csrrsi rd, csr, uimm[4:0] | t = CSRs[csr]; CSRs[csr] = t \| zext(uimm[4:0]); x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. | Control and Status Register Operations
| CSRRCI | csrrci rd, csr, uimm[4:0] | t = CSRs[csr]; CSRs[csr] = t & ∼zext(uimm[4:0]); x[rd] = t | NONE | Attempts to access a non-existent CSR raise an illegal instruction exception. Attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions. | Reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written). If the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. | Control and Status Register Operations
|===
==== RV32Zcb Code Size Reduction Instructions
|===
| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name
| C.ZEXT.B | c.zext.b rd' | x[8 + rd'] = zext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It zero-extends the least-significant byte of the operand by inserting zeros into all of the bits more significant than 7. | Code Size Reduction Operations
| C.SEXT.B | c.sext.b rd' | x[8 + rd'] = sext(x[8 + rd'][7:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations
| C.ZEXT.H | c.zext.h rd' | x[8 + rd'] = zext(x[8 + rd'][15:0]) | NONE | NONE | This instruction takes a single source/destination operand. It zero-extends the least-significant halfword of the operand by inserting zeros into all of the bits more significant than 15. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations
| C.SEXT.H | c.sext.h rd' | x[8 + rd'] = sext(x[8 + rd'][15:0]) | NONE | NONE | This instruction takes a single source/destination operand. It sign-extends the least-significant halfword in the operand by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support. | Code Size Reduction Operations
| C.NOT | c.not rd' | x[8 + rd'] = x[8 + rd'] ^ -1 | NONE | NONE | This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register. | Code Size Reduction Operations
| C.MUL | c.mul rd', rs2' | x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0] | NONE | NONE | performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rd' and rs2' treated as signed numbers). It also requires M extension support. | Code Size Reduction Operations
| C.LHU | c.lhu rd', uimm(rs1') | x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0]) | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended and is written to rd'. | Code Size Reduction Operations
| C.LH | c.lh rd', uimm(rs1') | x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0]) | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended and is written to rd'. | Code Size Reduction Operations
| C.LBU | c.lbu rd', uimm(rs1') | x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0]) | NONE | NONE | This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended and is written to rd'. | Code Size Reduction Operations
| C.SH | c.sh rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2'] | NONE | an exception raised if the memory address isn't aligned (2-byte boundary). | This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | Code Size Reduction Operations
| C.SB | c.sb rs2', uimm(rs1') | M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2'] | NONE | NONE | This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm. | Code Size Reduction Operations
|===
==== RVZba Address generation instructions
|===
| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name
| ADD.UW | add.uw rd, rs1, rs2 | X(rd) = rs2 + EXTZ(X(rs1)[31..0]) | NONE | NONE | This instruction performs an XLEN-wide addition between rs2 and the zero-extended least-significant word of rs1. | Address generation instructions
| SH1ADD | sh1add rd, rs1, rs2 | X(rd) = X(rs2) + (X(rs1) << 1) | NONE | NONE | This instruction shifts rs1 to the left by 1 bit and adds it to rs2. | Address generation instructions
| SH1ADD.UW | sh1add.uw rd, rs1, rs2 | X(rd) = rs2 + (EXTZ(X(rs1)[31..0]) << 1) | NONE | NONE | This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 1 place. | Address generation instructions
| SH2ADD | sh2add rd, rs1, rs2 | X(rd) = X(rs2) + (X(rs1) << 2) | NONE | NONE | This instruction shifts rs1 to the left by 2 bit and adds it to rs2. | Address generation instructions
| SH2ADD.UW | sh2add.uw rd, rs1, rs2 | X(rd) = rs2 + (EXTZ(X(rs1)[31..0]) << 2) | NONE | NONE | This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 2 places. | Address generation instructions
| SH3ADD | sh3add rd, rs1, rs2 | X(rd) = X(rs2) + (X(rs1) << 3) | NONE | NONE | This instruction shifts rs1 to the left by 3 bit and adds it to rs2. | Address generation instructions
| SH3ADD.UW | sh3add.uw rd, rs1, rs2 | X(rd) = rs2 + (EXTZ(X(rs1)[31..0]) << 3) | NONE | NONE | This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 3 places. | Address generation instructions
| SLLI.UW | slli.uw rd, rs1, imm | X(rd) = (EXTZ(X(rs)[31..0]) << imm) | NONE | NONE | This instruction takes the least-significant word of rs1, zero-extends it, and shifts it left by the immediate. | Address generation instructions
|===
==== RVZbb Basic bit-manipulation
|===
| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name
| ANDN | andn rd, rs1, rs2 | X(rd) = X(rs1) & ~X(rs2) | NONE | NONE | Performs bitwise AND operation between rs1 and bitwise inversion of rs2. | Logical_with_negate
| ORN | orn rd, rs1, rs2 | X(rd) = X(rs1) \| ~X(rs2) | NONE | NONE | Performs bitwise OR operation between rs1 and bitwise inversion of rs2. | Logical_with_negate
| XNOR | xnor rd, rs1, rs2 | X(rd) = ~(X(rs1) ^ X(rs2)) | NONE | NONE | Performs bitwise XOR operation between rs1 and rs2, then complements the result. | Logical_with_negate
| CLZ | clz rd, rs | if [x[i]] == 1 then return(i) else return -1 | NONE | NONE | Counts leading zero bits in rs. | Count_leading_trailing_zero_bits
| CTZ | ctz rd, rs | if [x[i]] == 1 then return(i) else return xlen; | NONE | NONE | Counts trailing zero bits in rs. | Count_leading_trailing_zero_bits
| CLZW | clzw rd, rs | if [x[i]] == 1 then return(i) else return -1 | NONE | NONE | Counts leading zero bits in the least-significant word of rs. | Count_leading_trailing_zero_bits
| CTZW | ctzw rd, rs | if [x[i]] == 1 then return(i) else return 32; | NONE | NONE | Counts trailing zero bits in the least-significant word of rs. | Count_leading_trailing_zero_bits
| CPOP | cpop rd, rs | if rs[i] == 1 then bitcount = bitcount + 1 else () | NONE | NONE | Counts set bits in rs. | Count_population
| CPOPW | cpopw rd, rs | if rs[i] == 0b1 then bitcount = bitcount + 1 else () | NONE | NONE | Counts set bits in the least-significant word of rs. | Count_population
| MAX | max rd, rs1, rs2 | if rs1_val <_s rs2_val then rs2_val else rs1_val | NONE | NONE | Returns the larger of two signed integers. | Integer_minimum_maximum
| MAXU | maxu rd, rs1, rs2 | if rs1_val <_u rs2_val then rs2_val else rs1_val | NONE | NONE | Returns the larger of two unsigned integers. | Integer_minimum_maximum
| MIN | min rd, rs1, rs2 | if rs1_val <_s rs2_val then rs1_val else rs2_val | NONE | NONE | Returns the smaller of two signed integers. | Integer_minimum_maximum
| MINU | minu rd, rs1, rs2 | if rs1_val <_u rs2_val then rs1_val else rs2_val | NONE | NONE | Returns the smaller of two unsigned integers. | Integer_minimum_maximum
| SEXT.B | sext.b rd, rs | X(rd) = EXTS(X(rs)[7..0]) | NONE | NONE | Sign-extends the least-significant byte in the source to XLEN. | Sign_and_zero_extension
| SEXT.H | sext.h rd, rs | X(rd) = EXTS(X(rs)[15..0]) | NONE | NONE | Sign-extends the least-significant halfword in rs to XLEN. | Sign_and_zero_extension
| ZEXT.H | zext.h rd, rs | X(rd) = EXTZ(X(rs)[15..0]) | NONE | NONE | Zero-extends the least-significant halfword of the source to XLEN. | Sign_and_zero_extension
| ROL | rol rd, rs1, rs2 | (X(rs1) << log2(XLEN)) \| (X(rs1) >> (xlen - log2(XLEN))) | NONE | NONE | Performs a rotate left of rs1 by the amount in least-significant log2(XLEN) bits of rs2. | Bitwise_rotation
| ROR | ror rd, rs1, rs2 | (X(rs1) >> log2(XLEN)) \| (X(rs1) << (xlen - log2(XLEN))) | NONE | NONE | Performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of rs2. | Bitwise_rotation
| RORI | rori rd, rs1, shamt | (X(rs1) >> log2(XLEN)) \| (X(rs1) << (xlen - log2(XLEN))) | NONE | NONE | Performs a rotate right of rs1 by the amount in least-significant log2(XLEN) bits of shamt. | Bitwise_rotation
| ROLW | rolw rd, rs1, rs2 | EXTS((rs1 << X(rs2)[4..0]) \| (rs1 >> (32 - X(rs2)[4..0]))) | NONE | NONE | Performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. | Bitwise_rotation
| RORIW | roriw rd, rs1, shamt | (rs1_data >> shamt[4..0]) \| (rs1_data << (32 - shamt[4..0])) | NONE | NONE | Performs a rotate right on the least-significant word of rs1 by the amount in least-significant log2(XLEN) bits of shamt. | Bitwise_rotation
| RORW | rorw rd, rs1, rs2 | (rs1 >> X(rs2)[4..0]) \| (rs1 << (32 - X(rs2)[4..0])) | NONE | NONE | Performs a rotate right on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. | Bitwise_rotation
| ORC.b | orc.b rd, rs | if { input[(i + 7)..i] == 0 then 0b00000000 else 0b11111111 | NONE | NONE | Sets the bits of each byte in rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set. | OR_Combine
| REV8 | rev8 rd, rs | output[i..(i + 7)] = input[(j - 7)..j] | NONE | NONE | Reverses the order of the bytes in rs. | Byte_reverse
|===
==== RVZbc Carry-less multiplication
|===
| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name
| CLMUL | clmul rd, rs1, rs2 | foreach (i from 1 to xlen by 1) { output = if ((rs2 >> i) & 1) then output ^ (rs1 << i); else output;} | NONE | NONE | clmul produces the lower half of the 2.XLEN carry-less product. | Carry-less multiplication Operations
| CLMULH | clmulh rd, rs1, rs2 | foreach (i from 1 to xlen by 1) { output = if ((rs2_val >> i) & 1) then output ^ (rs1_val >> (xlen - i)) else output} | NONE | NONE | clmulh produces the upper half of the 2.XLEN carry-less product. | Carry-less multiplication Operations
| CLMULR | clmulr rd, rs1, rs2 | foreach (i from 0 to (xlen - 1) by 1) { output = if ((rs2_val >> i) & 1) then output ^ (rs1_val >> (xlen - i - 1)) else output} | NONE | NONE | clmulr produces bits 2.XLEN-2:XLEN-1 of the 2.XLEN carry-less product. | Carry-less multiplication Operations
|===
==== RVZbs Single bit Instructions
|===
| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name
| BCLR | bclr rd, rs1, rs2 | X(rd) = X(rs1) & ~(1 << (X(rs2) & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit cleared at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. | Single_bit_Operations
| BCLRI | bclri rd, rs1, shamt | X(rd) = X(rs1) & ~(1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit cleared at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations
| BEXT | bext rd, rs1, rs2 | X(rd) = (X(rs1) >> (X(rs2) & (XLEN - 1))) & 1 | NONE | NONE | This instruction returns a single bit extracted from rs1 at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. | Single_bit_Operations
| BEXTI | bexti rd, rs1, shamt | X(rd) = (X(rs1) >> (shamt & (XLEN - 1))) & 1 | NONE | NONE | This instruction returns a single bit extracted from rs1 at the index specified in rs2. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations
| BINV | binv rd, rs1, rs2 | X(rd) = X(rs1) ^ (1 << (X(rs2) & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit inverted at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. | Single_bit_Operations
| BINVI | binvi rd, rs1, shamt | X(rd) = X(rs1) ^ (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit inverted at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations
| BSET | bset rd, rs1, rs2 | X(rd) = X(rs1) \| (1 << (X(rs2) & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. | Single_bit_Operations
| BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) \| (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations
|===

1
config/gen_from_riscv_config/cv32a60x/spike/spike.yaml
View file

@ -13,7 +13,6 @@ spike_param_tree:
core_configs:
-
isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs_xcvxif
extensions: cv32a60x
boot_addr: 2147483648
marchid_override_mask: 0xFFFFFFFF
marchid_override_value: 0x3

8
config/gen_from_riscv_config/scripts/libs/csr_updater.py
View file

@ -26,8 +26,9 @@ def csr_formatter(srcfile, customfile, debugfile, modifile):
# Read original dictionary from YAML source file
with open(srcfile, "r", encoding="utf-8") as file:
original_dict = yaml.safe_load(file)
with open(customfile, "r", encoding="utf-8") as file:
custom_dict = yaml.safe_load(file)
if customfile:
with open(customfile, "r", encoding="utf-8") as file:
custom_dict = yaml.safe_load(file)
debug_dict = {}
riscv_config_data = original_dict.copy()
if debugfile is not None:
@ -35,7 +36,8 @@ def csr_formatter(srcfile, customfile, debugfile, modifile):
debug_dict = yaml.safe_load(file)
if debug_dict["hart0"]["debug_mode"]:
riscv_config_data["hart0"].update(debug_dict["hart0"])
riscv_config_data["hart0"].update(custom_dict["hart0"])
if customfile:
riscv_config_data["hart0"].update(custom_dict["hart0"])
update_dict = {}
if modifile is not None:
with open(modifile, "r", encoding="utf-8") as file:

2
config/gen_from_riscv_config/scripts/libs/spike_updater.py
View file

@ -1,4 +1,4 @@
# Copyright 2024 Thales DIS France SAS
# Copyright 2025 Thales DIS France SAS
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.

9
config/gen_from_riscv_config/scripts/libs/utils.py
View file

@ -682,8 +682,7 @@ class InstadocBlock(InstructionBlockClass):
InstrExtList = [reg.Extension_Name for reg in self.Instructionlist]
r += "////\n"
r += " Copyright (c) 2024 OpenHW Group\n"
r += " Copyright (c) 2024 Thales\n"
r += " Copyright (c) 2025 Thales DIS France SAS\n"
r += " SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n"
r += " Author: Abdessamii Oukalrazqou\n"
r += "////\n\n"
@ -696,7 +695,7 @@ class InstadocBlock(InstructionBlockClass):
for i, _ in enumerate(InstrNameList):
r += "|%s | %s | %s\n"%(str(InstrExtList[i]),
str(InstrNameList[i]),
str(InstrDescrList[i]).replace('\n',''))
str(InstrDescrList[i]).replace('\n',' '))
r += "|===\n\n"
for reg in self.Instructionlist:
@ -704,7 +703,7 @@ class InstadocBlock(InstructionBlockClass):
if len(reg.Name) > 0:
r += "==== %s\n\n"%reg.key
r += "|===\n"
r += "| Name | Format | Pseudocode|Invalid_values | Exception_raised | Description| Op Name\n\n"
r += "| Name | Format | Pseudocode|Invalid_values | Instruction_exception | Instruction_description | Op Name\n\n"
for fieldIndex in list(range(len(reg.Name))):
_line = [
@ -718,7 +717,7 @@ class InstadocBlock(InstructionBlockClass):
_line.append(reg.OperationName[fieldIndex])
for col in _line:
r +="| %s "%col.replace('\n','')
r +="| %s "%col.replace('\n',' ')
r += "\n"
r += "|===\n\n"
return r

39
config/gen_from_riscv_config/templates/isa_template.yaml
View file

@ -32,7 +32,7 @@ RV32Zcb Code Size Reduction Instructions:
Exception_Raised: NONE
C.ZEXT.H:
Format: c.zext.h rd'
Description: >
Description: >
This instruction takes a single source/destination operand. It
zero-extends the least-significant halfword of the operand by inserting
zeros into all of the bits more significant than 15. It also requires
@ -90,7 +90,7 @@ RV32Zcb Code Size Reduction Instructions:
(2-byte boundary).
C.LBU:
Format: c.lbu rd', uimm(rs1')
Description: >
Description: >
This instruction loads a byte from the memory address formed by
adding rs1' to the zero extended immediate uimm. The resulting byte is
zero extended and is written to rd'.
@ -462,7 +462,7 @@ RV32C Compressed Instructions:
(4-byte boundary).
RV32M Multiplication and Division Instructions:
Description: >
the standard integer multiplication and division instruction
The standard integer multiplication and division instruction
extension, which is named “M” and contains instructions that multiply or
divide values held in two integer registers.
Subset_Name: M
@ -530,7 +530,7 @@ RV32M Multiplication and Division Instructions:
Exception_Raised: NONE
RV32Zicond Integer Conditional Instructions:
Description: >
The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destination operand).
The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destination operand).
Using these instructions, branchless sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion,
special provisions during the decoding of architectural instructions, or other microarchitectural provisions
Subset_Name: Zicond
@ -548,7 +548,7 @@ RV32Zicond Integer Conditional Instructions:
Exception_Raised: NONE
CZERO.NEZ:
Format: czero.nez rd, rs1, rs2
Description: >
Description: >
This instruction behaves as if there is a conditional branch
dependent on rs2 being not equal to zero, wherein it branches to code
that writes a 0 into rd when the equivalence is true, and otherwise
@ -595,7 +595,7 @@ RV32Zicsr Control and Status Register Instructions:
instruction exceptions on accesses to read-only CSRs.
Pseudocode: t = CSRs[csr]; CSRs[csr] = t | x[rs1]; x[rd] = t
Invalid_Values: NONE
Exception_Raised: >
Exception_Raised: >
Attempts to access a non-existent CSR raise an illegal
instruction exception. Attempts to access a CSR without appropriate
privilege level or to write a read-only register also raise illegal
@ -908,7 +908,7 @@ RVZbs Single bit Instructions:
Invalid_Values: NONE
Exception_Raised: NONE
RVZbc Carry-less multiplication:
Description : |
Description : |
Carry-less multiplication is the multiplication in the polynomial ring over GF(2).
clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product.
clmulr produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product.
@ -1011,8 +1011,8 @@ RVZba Address generation instructions:
Exception_Raised: NONE
RV32I Base Integer Instructions:
Description : |
the base integer instruction set, also known as the 'RV32I' or 'RV64I' instruction set , depending on the address space size, provides the core functionality required for general-purpose computing .
it includes instructions for arithmetic, logical, and control operations, as well as memory access
The base integer instruction set, also known as the 'RV32I' or 'RV64I' instruction set, depending on the address space size, provides the core functionality required for general-purpose computing.
It includes instructions for arithmetic, logical, and control operations, as well as memory access
and manipulation
Subset_Name : I
Instructions :
@ -1262,18 +1262,13 @@ RV32I Base Integer Instructions:
Description: "cause control to be transferred back to a debugging environment."
Pseudocode: "RaiseException(Breakpoint)"
Invalid_Values: "NONE"
Exception_Raised: "Raise a Breakpoint exception.rmat: c.sext.b rd"
Description: >
This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support.
Pseudocode: x[8 + rd'] = sext(x[8 + rd'][7:0])
Invalid_Values: NONE
Exception_Raised: NONE
Exception_Raised: Raise a Breakpoint exception.
RVZbb Basic bit-manipulation:
Description : |
The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction.
The bit-manipulation (bitmanip) extension collection is comprised of several component extensions to the base RISC-V architecture that are intended to provide some combination of code size reduction, performance improvement, and energy reduction.
While the instructions are intended to have general use, some instructions are more useful in some domains than others. Hence, several smaller bitmanip extensions are provided. Each of these smaller extensions is grouped by common function and use case, and each has its own Zb*-extension name.
Subset_Name : Zbb
Instructions :
Subset_Name : Zbb
Instructions :
Logical_with_negate:
ANDN:
Format: andn rd, rs1, rs2
@ -1287,7 +1282,7 @@ RVZbb Basic bit-manipulation:
Pseudocode: X(rd) = X(rs1) | ~X(rs2)
Invalid_Values: NONE
Exception_Raised: NONE
XNOR:
XNOR:
Format: xnor rd, rs1, rs2
Description: Performs bitwise XOR operation between rs1 and rs2, then complements the result.
Pseudocode: X(rd) = ~(X(rs1) ^ X(rs2))
@ -1306,13 +1301,13 @@ RVZbb Basic bit-manipulation:
Pseudocode: if [x[i]] == 1 then return(i) else return xlen;
Invalid_Values: NONE
Exception_Raised: NONE
CLZW:
CLZW:
Format: clzw rd, rs
Description: Counts leading zero bits in the least-significant word of rs.
Pseudocode: if [x[i]] == 1 then return(i) else return -1
Invalid_Values: NONE
Exception_Raised: NONE
CTZW:
CTZW:
Format: ctzw rd, rs
Description: Counts trailing zero bits in the least-significant word of rs.
Pseudocode: if [x[i]] == 1 then return(i) else return 32;
@ -1395,7 +1390,7 @@ RVZbb Basic bit-manipulation:
Pseudocode: (X(rs1) >> log2(XLEN)) | (X(rs1) << (xlen - log2(XLEN)))
Invalid_Values: NONE
Exception_Raised: NONE
ROLW:
Format: rolw rd, rs1, rs2
Description: Performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.

1217
config/gen_from_riscv_config/updaters/cv32a60x/csr_updater.yaml Normal file
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16
config/gen_from_riscv_config/updaters/cv32a60x/isa_updater.yaml Normal file
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@ -0,0 +1,16 @@
# Copyright (c) 2024 OpenHW Group
# Copyright (c) 2025 Thales DIS France SAS
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# Author: Abdessamii Oukalrazqou
# Enable and disable extension
Zicond : False
Zcb : True
Zcmp : False
Zbb : False

27
config/gen_from_riscv_config/updaters/cv32a60x/spike_updater.yaml Normal file
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@ -0,0 +1,27 @@
# Copyright (c) 2024 OpenHW Group
# Copyright (c) 2025 Thales DIS France SAS
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# Author: Abdessamii Oukalrazqou
cores:
- isa: rv32imc_zba_zbb_zbs_zbc_zicsr_zifencei
boot_addr: 0x80000000
marchid: 0x3
misa_we: false
misa_we_enable: true
pmpaddr0: 0x0
pmpcfg0: 0x0
pmpregions: 0x40
usable_pmpregions : 0x8
priv: M
status_fs_field_we: false
status_fs_field_we_enable: false
status_vs_field_we: false
status_vs_field_we_enable: false
priv: M
misa_we: false
mstatus_write_mask: 0x00000088
mstatus_override_mask: 0x00001800
mtval_write_mask: 0x00000000
unified_traps: true

13
config/riscv-config/Makefile
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@ -20,10 +20,17 @@ RVCONFIG_DIR ?= $(shell pwd)/../../vendor/riscv/riscv-config
TARGET ?= cv32a65x
# List of component files (inputs and processed)
COMPONENTS = isa custom platform
COMPONENTS ?= isa custom platform
ifeq ($(findstring custom, $(COMPONENTS)),custom)
CUSTOM_SPEC = -cspec $(SPEC_DIR)/custom_spec.yaml
endif
SPEC_DIR = $(TARGET)/spec
GEN_DIR = $(TARGET)/generated
RVCONFIG_INPUTS = $(patsubst %,$(SPEC_DIR)/%_spec.yaml,$(COMPONENTS))
# NOTE: names of the generated files are imposed by riscv-config.
RVCONFIG_OUTPUTS= $(patsubst %,$(GEN_DIR)/%_spec_checked.yaml,$(COMPONENTS))
OUTPUT_FILES = $(patsubst %,$(GEN_DIR)/%_gen.yaml,$(COMPONENTS))
@ -39,8 +46,8 @@ $(RVCONFIG_OUTPUTS): $(RVCONFIG_INPUTS) Makefile
python3 -m riscv_config.main \
--work_dir $(GEN_DIR) \
-ispec $(SPEC_DIR)/isa_spec.yaml \
-cspec $(SPEC_DIR)/custom_spec.yaml \
-pspec $(SPEC_DIR)/platform_spec.yaml
-pspec $(SPEC_DIR)/platform_spec.yaml \
$(CUSTOM_SPEC)
clean: distclean
$(RM) $(OUTPUT_FILES)

67
config/riscv-config/cv32a60x/generated/custom_gen.yaml
View file

@ -1,67 +0,0 @@
# Copyright 2024 Thales DIS France SAS
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Original Author: Zbigniew CHAMSKI - Thales
hart_ids: [0]
hart0:
icache:
reset-val: 0x1
rv64:
accessible: false
rv32:
accessible: true
icache:
implemented: true
type:
rw: true
description: bit for cache-enable of instruction cache
msb: 0
lsb: 0
shadow:
shadow_type:
fields:
- icache
-
-
- 1
- 31
description: the register controls the operation of the i-cache unit.
address: 0x7c0
priv_mode: M
dcache:
reset-val: 0x1
rv64:
accessible: false
rv32:
accessible: true
dcache:
implemented: true
type:
rw: true
description: bit for cache-enable of data cache
shadow:
shadow_type:
msb: 0
lsb: 0
fields:
- dcache
-
-
- 1
- 31
description: the register controls the operation of the d-cache unit.
address: 0x7c1
priv_mode: M

39
config/riscv-config/cv32a60x/spec/custom_spec.yaml
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@ -14,42 +14,3 @@
#
# Original Author: Zbigniew CHAMSKI - Thales
hart_ids: [0]
hart0:
icache:
reset-val: 0x1
rv64:
accessible: false
rv32:
accessible: true
icache:
implemented: true
type:
rw: true
description: bit for cache-enable of instruction cache
msb: 0
lsb: 0
shadow:
shadow_type:
description: the register controls the operation of the i-cache unit.
address: 0x7c0
priv_mode: M
dcache:
reset-val: 0x1
rv64:
accessible: false
rv32:
accessible: true
dcache:
implemented: true
type:
rw: true
description: bit for cache-enable of data cache
shadow:
shadow_type:
msb: 0
lsb: 0
description: the register controls the operation of the d-cache unit.
address: 0x7c1
priv_mode: M

2
core/include/config_pkg.sv
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@ -235,7 +235,7 @@ package config_pkg;
bit unsigned UseSharedTlb;
// MMU depth of shared TLB
int unsigned SharedTlbDepth;
// OBI version compliance, 0 mean non compliant -> best performance
// OBI version compliance, 0 means not compliant -> best performance
int unsigned ObiVersion;
// Configuration defines cva6_pipeline module as top instead of cva6 (no cache and OBI instead of AXI)
bit PipelineOnly;

52
docs/01_cva6_user/user_cfg_doc.rst
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@ -20,6 +20,10 @@
- ``int unsigned``
- General Purpose Register Size (in bits)
* - ``VLEN``
- ``int unsigned``
- Virtual address Size (in bits)
* - ``RVA``
- ``bit``
- Atomic RISC-V extension
@ -28,6 +32,10 @@
- ``bit``
- Bit manipulation RISC-V extension
* - ``ZKN``
- ``bit``
- Scalar Cryptography RISC-V entension
* - ``RVV``
- ``bit``
- Vector RISC-V extension
@ -48,6 +56,10 @@
- ``bit``
- Zcmp RISC-V extension
* - ``RVZCMT``
- ``bit``
- Zcmt RISC-V extension
* - ``RVZiCond``
- ``bit``
- Zicond RISC-V extension
@ -56,6 +68,10 @@
- ``bit``
- Zicntr RISC-V extension
* - ``RVZifencei``
- ``bit``
- Zifencei RISC-V extension
* - ``RVZihpm``
- ``bit``
- Zihpm RISC-V extension
@ -100,6 +116,10 @@
- ``bit``
- User mode
* - ``SoftwareInterruptEn``
- ``bit``
- Software interrupts are enabled
* - ``DebugEn``
- ``bit``
- Debug support
@ -140,6 +160,10 @@
- ``bit [63:0]``
- PMP CSR read-only bits
* - ``PMPNapotEn``
- ``bit``
- PMP NA4 and NAPOT mode enable
* - ``NrNonIdempotentRules``
- ``int unsigned``
- PMA non idempotent rules number
@ -180,6 +204,10 @@
- ``bit``
- CV-X-IF coprocessor interface enable
* - ``CoproType``
- ``copro_type_t``
- Coprocessor type
* - ``NOCType``
- ``noc_type_e``
- NOC bus type
@ -206,7 +234,7 @@
* - ``MemTidWidth``
- ``int unsigned``
- TODO
- Transaction ID
* - ``IcacheByteSize``
- ``int unsigned``
@ -240,6 +268,14 @@
- ``int unsigned``
- Data cache line width
* - ``DcacheFlushOnFence``
- ``bit``
- Data cache flush on fence
* - ``DcacheInvalidateOnFlush``
- ``bit``
- Data cache invalidate on flush
* - ``DataUserEn``
- ``int unsigned``
- User field on data bus enable
@ -258,7 +294,11 @@
* - ``FpgaEn``
- ``bit``
- Is FPGA optimization of CV32A6
- Is FPGA optimization of CV32A6 for Xilinx and Altera
* - ``FpgaAlteraEn``
- ``bit``
- Is FPGA optimization for Altera FPGA
* - ``TechnoCut``
- ``bit``
@ -319,3 +359,11 @@
* - ``SharedTlbDepth``
- ``int unsigned``
- MMU depth of shared TLB
* - ``ObiVersion``
- ``int unsigned``
- OBI version compliance, 0 means not compliant -> best performance
* - ``PipelineOnly``
- ``bit``
- Configuration defines cva6_pipeline module as top instead of cva6 (no cache and OBI instead of AXI)

1
docs/07_cv32a60x/design/.gitignore vendored Normal file
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@ -0,0 +1 @@
build

7
docs/07_cv32a60x/design/Makefile Normal file
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@ -0,0 +1,7 @@
# Copyright (c) 2025 OpenHW Group
# Copyright (c) 2025 Thales DIS France SAS
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
# Author: Jean-Roch COULON - Thales
CONFIG := cv32a60x
include ../../design/build.mk

20
docs/07_cv32a60x/design/design.rst Normal file
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@ -0,0 +1,20 @@
..
Copyright (c) 2025 OpenHW Group
Copyright (c) 2025 Thales DIS France SAS
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
Author: Jean-Roch COULON - Thales
CV32A65X DESIGN DOCUMENT
========================
.. raw:: html
<style>
.wy-nav-content {
max-width: none;
}
</style>
.. raw:: html
:file: design-cv32a60x.html

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7
docs/design/build.mk
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@ -15,6 +15,11 @@ current_dir = $(shell pwd)
# Path of current file, intended to be included by a configuration subfolder
design_dir := $(dir $(lastword $(MAKEFILE_LIST)))
# custom_gen.yaml is optional. Do not pass it as cmdline arg if absent.
ifneq ($(wildcard ../riscv-config/$(CONFIG)/generated/custom_gen.yaml),)
CUSTOM_CSR_ARG = -c ../riscv-config/$(CONFIG)/generated/custom_gen.yaml
endif
all: design-pdf design-html
setup:
@ -27,7 +32,7 @@ setup:
cp -rf source/* build/source
cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/$(CONFIG)/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/$(CONFIG)/isa_updater.yaml -t $(CONFIG) -f adoc
cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/$(CONFIG)/generated/isa_gen.yaml -c ../riscv-config/$(CONFIG)/generated/custom_gen.yaml -m updaters/$(CONFIG)/csr_updater.yaml -t $(CONFIG) -f adoc
cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/$(CONFIG)/generated/isa_gen.yaml $(CUSTOM_CSR_ARG) -m updaters/$(CONFIG)/csr_updater.yaml -t $(CONFIG) -f adoc
cp -r $(design_dir)/../../config/gen_from_riscv_config/$(CONFIG)/* build/source
cd ../.. && python3 scripts/spec_builder.py --target $(CONFIG) --gen-config $(current_dir)/build/source/config.adoc --gen-parameters $(current_dir)/build/source/parameters.adoc --gen-ports $(current_dir)/build/source

164
docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc
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@ -5,6 +5,7 @@ CV-X-IF Interface and Coprocessor
The CV-X-IF interface of CVA6 allows to extend its supported instruction
set with external coprocessors.
ifeval::["{ohg-config}" != "CV32A60X"]
_Applicability of this chapter to configurations:_
[cols=",",options="header",]
@ -14,6 +15,7 @@ _Applicability of this chapter to configurations:_
|CV32A60X |CV-X-IF included
|CV64A6_MMU |CV-X-IF included
|=============================
endif::[]
[[cv-x-if-interface-specification]]
CV-X-IF interface specification
@ -25,6 +27,7 @@ Description
This design specification presents global functionalities of
Core-V-eXtension-Interface (XIF, CVXIF, CV-X-IF, X-interface) in the CVA6 core.
CVA6 implements version v1.0.0: Ratified Release.
[source,sourceCode,text]
@ -33,7 +36,7 @@ The CORE-V X-Interface is a RISC-V eXtension interface that provides a
generalized framework suitable to implement custom coprocessors and ISA
extensions for existing RISC-V processors.
--core-v-xif Readme, https://github.com/openhwgroup/core-v-xif
Refer to https://github.com/openhwgroup/core-v-xif GitHub repository
----
The specification of the CV-X-IF bus protocol can be found at [CV-X-IF].
@ -50,9 +53,9 @@ CV-X-IF aims to:
The coprocessor operates like another functional unit so it is connected
to the CVA6 in the execute stage.
Only the 3 mandatory interfaces from the CV-X-IF specification (issue, commit and result
Only the 5 mandatory interfaces from the CV-X-IF specification (compressed, issue, register, commit and result
) have been implemented.
Compressed interface, Memory Interface and Memory result interface are not yet
Memory Interface and Memory result interface are optional interfaces, they are not
implemented in the CVA6.
[[supported-parameters]]
@ -67,8 +70,7 @@ The following table presents CVXIF parameters supported by CVA6.
|*X_NUM_RS* |
int: 2 or 3 (configurable) +
* CV32A60X: 2
* CV32A65X: 2
* {ohg-config}: 2
|
[verse]
--
@ -79,8 +81,12 @@ be used by the eXtension interface
|*X_ID_WIDTH* |
int: 1 to 32 +
ifeval::["{ohg-config}" == "CV32A60X"]
* CV32A60X: 2
endif::[]
ifeval::["{ohg-config}" == "CV32A65X"]
* CV32A65X: 3
endif::[]
|
[verse]
--
@ -98,8 +104,7 @@ eXtension interface
|*X_RFR_WIDTH* |
int: `XLEN` (32 or 64) +
* CV32A60X: 32
* CV32A65X: 32
* {ohg-config}: 32
|
[verse]
--
@ -110,8 +115,7 @@ eXtension interface
|*X_RFW_WIDTH* |
int: `XLEN` (32 or 64) +
* CV32A60X: 32
* CV32A65X: 32
* {ohg-config}: 32
|
[verse]
--
@ -134,6 +138,9 @@ CV-X-IF Enabling
CV-X-IF can be enabled or disabled via the `CVA6ConfigCvxifEn` parameter in the SystemVerilog source code.
Never let the CV-X-IF interface unconnected with the `CVA6ConfigCvxifEn` parameter enabled.
[[illegal-instruction-decoding]]
Illegal instruction decoding
++++++++++++++++++++++++++++
@ -159,115 +166,75 @@ a third read port is added to the CVA6 general purpose register file.
Description of interface connections between CVA6 and Coprocessor
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
In CVA6 execute stage, there is a new functional unit dedicated to drive the CV-X-IF interfaces.
In CVA6 execute stage, there is a new functional unit dedicated to drive the CV-X-IF interfaces.
Here is _how_ and _to what_ CV-X-IF interfaces are connected to the CVA6.
* Issue interface::
** Request;;
*** [verse]
--
Operands are connected to `issue_req.rs` signals
--
*** [verse]
--
Scoreboard transaction id is connected to `issue_req.id` signal.
* Compressed interface:
** Request:
*** Undecoded illegal instruction is connected to `compressed_req.instruction`
*** Illegal compressed signal calculated from all compressed decoders (RVC, ZCMP, ZCMT) is connected to `compressed_req.valid`.
** Response:
*** if `compressed_resp.accept` is set during a transaction (i.e.
`compressed_valid` and `compressed_ready` are set), the offloaded compressed
instruction is accepted by the coprocessor and `compressed_resp.instruction`
contains its 32 bits equivalent for the coprocessor and sent to the
32 bits decoder.
*** if ``compressed_resp.accept`` is not set during a transaction, the instruction
is an illegal compressed instruction and will follow its path in the
decode stage. Typically, it will try to be decoded as a 32 bits instruction.
* Issue and register interface (Coupled):
** Request:
*** Operands are connected to `register.rs` signals
*** Scoreboard transaction id is connected to `issue_req.id` signal.
Therefore scoreboard ids and offloaded instruction ids are linked
together (equal in this implementation). It allows the CVA6 to do out
of order execution with the coprocessor in the same way as other
functional units.
--
*** [verse]
--
Undecoded instruction is connected to `issue_req.instruction`
--
*** [verse]
--
Valid signal for CVXIF functional unit is connected to
*** Undecoded instruction is connected to `issue_req.instruction`
*** Valid signal for CVXIF functional unit is connected to
`issue_req.valid`
--
*** [verse]
--
All `issue_req.rs_valid` signals are set to 1. The validity of source
registers is assured by the validity of valid signal sent from issue stage.
--
** Response;;
*** [verse]
--
If `issue_resp.accept` is set during a transaction (i.e. issue valid
*** Each `register.rs_valid` signal is set when its associated stall signal is not set.
*** `register_valid` is connected to `issue_valid` because Issue and Register
interface are coupled. (`X_ISSUE_REGISTER_SPLIT == 0`)
** Response:
*** If `issue_resp.accept` is set during a transaction (i.e. issue valid
and ready are set), the offloaded instruction is accepted by the coprocessor
and a result transaction will happen.
--
*** [verse]
--
If `issue_resp.accept` is not set during a transaction, the offloaded
*** If `issue_resp.accept` is not set during a transaction, the offloaded
instruction is illegal and an illegal instruction exception will be
raised as soon as no result transaction are written on the writeback bus.
--
* Commit interface::
** [verse]
--
Valid signal of commit interface is connected to the valid signal of
* Commit interface:
** Valid signal of commit interface is connected to the valid signal of
issue interface.
--
** [verse]
--
Id signal of commit interface is connected to issue interface id signal
** Id signal of commit interface is connected to issue interface id signal
(i.e. scoreboard id).
--
** [verse]
--
Killing of offload instruction is never set. (Unsupported feature)
--
** [verse]
--
Therefore all accepted offloaded instructions are commited to their
** Killing of offload instruction is never set. (Unsupported feature)
** Therefore all accepted offloaded instructions are commited to their
execution and no killing of instruction is possible in this implementation.
--
* Result interface::
** Request;;
*** [verse]
--
Ready signal of result interface is always set as CVA6 is always ready
* Result interface:
** Request:
*** Ready signal of result interface is always set as CVA6 is always ready
to take a result from coprocessor for an accepted offloaded instruction.
--
** Response;;
*** [verse]
--
Result response is directly connected to writeback bus of the CV-X-IF
** Response:
*** Result response is directly connected to writeback bus of the CV-X-IF
functionnal unit.
--
*** [verse]
--
Valid signal of result interface is connected to valid signal of
*** Valid signal of result interface is connected to valid signal of
writeback bus.
--
*** [verse]
--
Id signal of result interface is connected to scoreboard id of
*** Id signal of result interface is connected to scoreboard id of
writeback bus.
--
*** [verse]
--
Write enable signal of result interface is connected to a dedicated CV-X-IF WE
*** Write enable signal of result interface is connected to a dedicated CV-X-IF WE
signal in CVA6 which signals scoreboard if a writeback should happen
or not to the CVA6 register file.
--
*** [verse]
--
`exccode` and `exc` signal of result interface are connected to exception
*** `exccode` and `exc` signal of result interface are connected to exception
signals of writeback bus. Exception from coprocessor does not write
the `tval` field in exception signal of writeback bus.
--
*** [verse]
--
Three registers are added to hold illegal instruction information in
*** Three registers are added to hold illegal instruction information in
case a result transaction and a non-accepted issue transaction happen
in the same cycle. Result transactions will be written to the writeback
bus in this case having priority over the non-accepted instruction due
to being linked to an older offloaded instruction. Once the writeback
bus is free, an illegal instruction exception will be raised thanks to
information held in these three registers.
--
[[coprocessor-recommendations-for-use-with-cva6s-cv-x-if]]
Coprocessor recommendations for use with CVA6's CV-X-IF
@ -275,18 +242,16 @@ Coprocessor recommendations for use with CVA6's CV-X-IF
CVA6 supports all coprocessors supporting the CV-X-IF specification with the exception of :
* Coprocessor requiring the Memory interface and Memory result interface (not implemented in CVA6 yet).::
** All memory transaction should happen via the Issue interface, i.e. Load into CVA6 register file
* Coprocessor requiring the Memory interface and Memory result interface (not implemented in CVA6 yet).
** All memory transaction should happen via the Issue interface, i.e. Load into CVA6 register file
then initialize an issue transaction.
* Coprocessor requiring the Compressed interface (not implemented in CVA6 yet).::
** RISC-V Compressed extension (RVC) is already implemented in CVA6 User Space for custom compressed instruction
is not big enough to have RVC and a custom compressed extension.
* Stateful coprocessors.::
** CVA6 will commit on the Commit interface all its issue transactions. Speculation
informations are only kept in the CVA6 and speculation process is only done in CVA6.
The coprocessor shall be stateless otherwise it will not be able to revert its state if CVA6 kills an
* Stateful coprocessors.
** CVA6 will commit on the Commit interface all its issue transactions. Speculation
informations are only kept in the CVA6 and speculation process is only done in CVA6.
The coprocessor shall be stateless otherwise it will not be able to revert its state if CVA6 kills an
in-flight instruction (in case of mispredict or flush).
ifeval::["{ohg-config}" != "CV32A60X"]
[[how-to-use-cva6-without-cv-x-if-interface]]
How to use CVA6 without CV-X-IF interface
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@ -306,3 +271,4 @@ How to program a CV-X-IF coprocessor
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
_The team is looking for a contributor to write this section._
endif::[]

10
docs/design/design-manual/source/OBI.adoc Normal file
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@ -0,0 +1,10 @@
////
Copyright (c) 2025 OpenHW Group
Copyright (c) 2025 Thales DIS France SAS
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
Author: Jean-Roch COULON - Thales
////
[[axi]]
include::OBI_Interface.adoc[]

316
docs/design/design-manual/source/OBI_Interface.adoc Normal file
View file

@ -0,0 +1,316 @@
////
Copyright (c) 2025 OpenHW Group
Copyright (c) 2025 Thales DIS France SAS
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
Author: Yannick Casamatta - Thales
////
[[cva6_obi]]
OBI Bus interface
~~~~~~~~~~~~~~~~~
OBI Bus aims to connected CVA6 to the memory.
CVA6 implements 3 interfaces, one for fetch instruction and two interfaces for data handling, one dedicated to loading operations and the other to storing operations.
Each connection uses a bus interface that complies with the OBI 1.6 standard. A detailed explanation of the optional fields described by this standard is provided in the table below.
In order to understand how the OBI memory interface behaves in CVA6, it is necessary to read the OBI Protocol Specification (https://github.com/openhwgroup/obi/) and this chapter.
[[protocol-description]]
Protocol Description
^^^^^^^^^^^^^^^^^^^^
OBI is a point-to-point protocol (between manager and subordinate)
An OBI link consists of two channels:
* The address channel, called the A channel.
* The response channel, called the R channel
OBI transaction consists of two transfers:
* An address phase transfer over the A channel.
* A response phase transfer over the R channel.
The address phase transfer is as follows:
* The manager indicates the validity of its address phase signals (i.e. addr, wdata, we, be, auser, aid, mid, wuser, prot, memtype, dbg, atop, achk) by settings its request (req) high.
* The subordinate indicates its readiness to accept the address phase signals by setting grant (gnt) high.
* The address phase of a transaction starts in the cycle in which req goes high and completes on the rising clk edge when both req and gnt are high.
The response phase transfer is as follows:
* After a granted request (in the A channel), the subordinate indicates the validity of its response phase signals (i.e. rdata, err, ruser, rid, exokay, rchk) by setting rvalid high.
* The manager indicates its readiness to accept the response phase signals by setting rready high.
* The response phase of a transaction starts in the cycle in which rvalid goes high and completes on the rising clk edge when both rvalid and rready are high.
[[cva6-implem]]
CVA6 implementation
^^^^^^^^^^^^^^^^^^^
All OBI buses for FETCH, LOAD, and STORE operations have a data size of 32 bits.
The Fetch interface performs only full BE accesses.
The Fetch and Load interfaces are only capable of read accesses.
The Store interface is exclusively for write accesses.
CVA6 is always ready to accept a response on channel R, so the rrready signal is always high.
The Fetch and Load interfaces do not generate outstanding accesses.
The Store interface does not use channel R. Therefore, the depth of outstanding accesses depends on the subordinate.
The error flag is not used at all.
Parity signal support is partial. Parity signals reqpar and rreadypar are generated as specified by the standard, but gntpar and rvalidpar are currently not checked by CVA6.
Checksum signals achk and rchk are not supported.
All user data signals (auser, wuser, ruser) are not used.
CVA6 does not support atomic operations, so exokay and atom are not used.
CVA6 does not have a Physical Memory Attribution (PMA), so cacheable or bufferable regions are not defined. As a consequence, memtype always 0.
prot[0] is driven to indicate the type of access: FETCH for the Fetch interface and DATA for the LOAD/STORE interfaces.
As only Machine mode is available in CVA6, prot[2:1] is statically at b'11' (Machine Mode).
The master identifier "Mid" is set to 0.
The transaction identifiers aid and rid signals are only 1-bit size. Even though there are no outstanding reads available, rid must be driven by the subordinate in compliance with the standard (rid = aid).
[[obi-port-list-a]]
Port list channel A
^^^^^^^^^^^^^^^^^^^
[cols=",,,,,",options="header",]
|===
|
|
|Fetch
|Load
|Store
|
|req
|OUTPUT
|used
|used
|used
|Address transfer request. req=1 signals the availability of valid address phase signals.
|gnt
|INPUT
|used
|used
|used
|Grant. Ready to accept address transfer. Address transfer is accepted on rising clk with req=1 and gnt=1.
|addr[]
|OUTPUT
|used
|used
|used
|Address
|we
|OUTPUT
|used
|used
|used
|Write Enable, high for writes, low for reads.
|be[3:0]
|OUTPUT
|used (always Full)
|used
|used
|Byte Enable. Is set for the bytes to write/read.
|wdata[31:0]
|OUTPUT
|0 (default)
|0 (default)
|used
|Write data. Only valid for write transactions. Undefined for read transactions.
|auser[0:0]
|OUTPUT
|0 (default)
|0 (default)
|0 (default)
|Address Phase User signals. Valid for both read and write transactions.
|wuser[0:0]
|OUTPUT
|0 (default)
|0 (default)
|0 (default)
|Additional Address Phase User signals. Only valid for write transactions. Undefined for read transactions.
|aid[0:0]
|OUTPUT
|0 (default)
|0 (default)
|0 (default)
|Address Phase transaction identifier.
|atop[5:0]
|OUTPUT
|0 (default)
|0 (default)
|0 (default)
|Atomic Operation.
|memtype[0]
|OUTPUT
|0 (default)
|0 (default)
|0 (default)
|Memory type attributes
|memtype[1]
|OUTPUT
|0, no PMA
|0, no PMA
|0, no PMA
|Memory type attributes, cacheable flag.
|mid[0:0]
|OUTPUT
|0 (default)
|0 (default)
|0 (default)
|Manager ID.
|prot[0]
|OUTPUT
|FETCH only
|DATA only
|DATA only
|Protection attributes. Kind of access : 0 is FETCH, 1 is DATA
|prot[2:1]
|OUTPUT
|2'b11
|2'b11
|2'b11
|Protection attributes, Privilege Mode: 2'b11 is machine mode.
|dbg
|OUTPUT
|0 (default)
|0 (default)
|0 (default)
|Debug access.
|reqpar
|OUTPUT
|used
|used
|used
|Parity bit for req signal (odd parity).
|gntpar
|INPUT
|not used
|not used
|not used
|Parity bit for gnt signal (odd parity).
|achk[0:0]
|OUTPUT
|tied at zero
|tied at zero
|tied at zero
|Checksum for address phase signals (except achk itself).
|===
[[obi-port-list-r]]
Port list channel R
^^^^^^^^^^^^^^^^^^^
[cols=",,,,,",options="header",]
|===
|
|
|Fetch
|Load
|Store
|
|rvalid
|INPUT
|used
|used
|used
|Response transfer request. rvalid=1 signals the availability of valid response phase signals. Used for both reads and writes.
|rready
|OUTPUT
|used
|used
|used
|Ready to accept response transfer. Response transfer is accepted on rising clk with rvalid=1 and rready=1.
|rdata[31:0]
|INPUT
|used
|used
|not used
|Read data. Only valid for read transactions. Undefined for write transactions.
|err
|INPUT
|not used
|not used
|not used
|Error.
|ruser[0:0]
|INPUT
|not used
|not used
|not used
|Response phase User signals. Only valid for read transactions. Undefined for write transactions.
|rid[0:0]
|INPUT
|used
|used
|used
|Response Phase transaction identifier.
|exokay
|INPUT
|not used
|not used
|not used
|Exclusive transaction okay.
|rvalidpar
|INPUT
|not used
|not used
|not used
|Parity bit for rvalid signal (odd parity).
|rreadypar
|OUTPUT
|used
|used
|used
|Parity bit for rready signal (odd parity).
|rchk[0:0]
|INPUT
|not used
|not used
|not used
|Checksum for address phase signals (except rchk itself).
|===

112
docs/design/design-manual/source/Traps_Interrupts_Exceptions.adoc
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@ -5,7 +5,11 @@ Traps, Interrupts, Exceptions
Traps are composed of interrupts and exceptions.
Interrupts are asynchronous events whereas exceptions are synchronous ones.
On one hand, interrupts are occuring independently of the instructions
(mainly raised by peripherals or debug module).
(mainly raised by peripherals
ifeval::[{DebugEn} == true]
or debug module
endif::[]
).
On the other hand, an instruction may raise exceptions synchronously.
[[raising-traps]]
@ -21,10 +25,24 @@ Configuration CSRs
CSRs having an effect on the core behaviour when a trap occurs are:
* `mstatus` and `sstatus`: several fields control the core behaviour like interrupt enable (`MIE`, `SIE`)
* `mtvec` and `stvec`: specifies the address of trap handler.
* `mstatus`
ifeval::[{RVS} == true]
and `sstatus`
endif::[]
: several fields control the core behaviour like interrupt enable (`MIE`
ifeval::[{RVS} == true]
, `SIE`
endif::[]
)
* `mtvec`
ifeval::[{RVS} == true]
and `stvec`
endif::[]
: specifies the address of trap handler.
ifeval::[{RVS} == true]
* `medeleg`: specifies which exceptions can be handled by a lower privileged mode (S-mode)
* `mideleg`: specifies which interrupts can be handled by a lower privileged mode (S-mode)
endif::[]
[[modified-csrs]]
Modified CSRs
@ -32,22 +50,54 @@ Modified CSRs
CSRs (or fields) updated by the core when a trap occurs are:
* `mstatus` or `sstatus`: several fields are updated like previous privilege mode (`MPP`, `SPP`), previous interrupt enabled (`MPIE`, SPIE``)
* `mepc` or `sepc`: updated with the virtual address of the interrupted instruction or the instruction raising the exception.
* `mcause` or `scause`: updated with a code indicating the event causing the trap.
* `mtval` or `stval`: updated with exception specific information like the faulting virtual address
* `mstatus`
ifeval::[{RVS} == true]
or `sstatus`
endif::[]
: several fields are updated like previous privilege mode (`MPP`
ifeval::[{RVS} == true]
, `SPP`
endif::[]
), previous interrupt enabled (`MPIE`
ifeval::[{RVS} == true]
, `SPIE`
endif::[]
)
* `mepc`
ifeval::[{RVS} == true]
or `sepc`
endif::[]
: updated with the
ifeval::[{MmuPresent} == true]
virtual
endif::[]
address of the interrupted instruction or the instruction raising the exception.
* `mcause`
ifeval::[{RVS} == true]
or `scause`
endif::[]
: updated with a code indicating the event causing the trap.
ifdef::archi-default,MTvalEn-true[]
* `mtval`
ifeval::[{RVS} == true]
or `stval`
endif::[]
: updated with exception specific information like the faulting virtual address
endif::[]
[[supported-exceptions]]
Supported exceptions
++++++++++++++++++++
The following exceptions are supported by the CVA6:
The following exceptions are supported by the {ohg-config}:
* instruction address misaligned
** control flow instruction with misaligned target
ifeval::[{NrPMPEntries} != 0]
* instruction access fault
** access to PMP region without execute permissions
endif::[]
* illegal instruction:
** unimplemented CSRs
@ -59,22 +109,31 @@ The following exceptions are supported by the CVA6:
** `LH` at 2n+1 address
** `LW` at 4n+1, 4n+2, 4n+3 address
ifeval::[{NrPMPEntries} != 0]
* load access fault
** access to PMP region without read permissions
endif::[]
* store/AMO address misaligned
** `SH` at 2n+1 address
** `SW` at 4n+1, 4n+2, 4n+3 address
ifeval::[{NrPMPEntries} != 0]
* store/AMO access fault
** access to PMP region without write permissions
endif::[]
ifeval::[{RVU} == true]
* environment call (`ECALL`) from U-mode
endif::[]
ifeval::[{RVS} == true]
* environment call (`ECALL`) from S-mode
endif::[]
* environment call (`ECALL`) from M-mode
ifeval::[{MmuPresent} == true]
* instruction page fault
* load page fault
@ -82,16 +141,25 @@ The following exceptions are supported by the CVA6:
* store/AMO page fault
** access to effective address without write permissions
endif::[]
ifeval::[{DebugEn} == true]
* debug request (custom) via debug interface
endif::[]
////
Note: all exceptions are supported except the ones linked to the hypervisor extension
////
[[trap-return]]
Trap return
^^^^^^^^^^^
Trap handler ends with trap return instruction (`MRET`, `SRET`). The behaviour of the CVA6 core depends on several CSRs.
Trap handler ends with trap return instruction (`MRET`
ifeval::[{RVS} == true]
, `SRET`
endif::[]
). The behaviour of the {ohg-config} core depends on several CSRs.
[[configuration-csrs-1]]
Configuration CSRs
@ -99,7 +167,15 @@ Configuration CSRs
CSRs having an effect on the core behaviour when returning from a trap are:
* `mstatus`: several fields control the core behaviour like previous privilege mode (`MPP`, `SPP`), previous interrupt enabled (`MPIE`, `SPIE`)
* `mstatus`: several fields control the core behaviour like previous privilege mode (`MPP`
ifeval::[{RVS} == true]
, `SPP`
endif::[]
), previous interrupt enabled (`MPIE`
ifeval::[{RVS} == true]
, `SPIE`
endif::[]
)
[[modified-csrs-1]]
Modified CSRs
@ -107,16 +183,24 @@ Modified CSRs
CSRs (or fields) updated by the core when returning from a trap are:
* `mstatus`: several fields are updated like interrupt enable (`MIE`, `SIE`), modify privilege (`MPRV`)
* `mstatus`: several fields are updated like interrupt enable (`MIE`
ifeval::[{RVS} == true]
, `SIE`
endif::[]
), modify privilege (`MPRV`)
[[interrupts]]
Interrupts
^^^^^^^^^^
* external interrupt: `irq_i` signal
ifeval::[{SoftwareInterruptEn} == true]
* software interrupt (inter-processor interrupt): `ipi_i` signal
endif::[]
* timer interrupt: `time_irq_i` signal
ifeval::[{DebugEn} == true]
* debug interrupt: `debug_req_i` signal
endif::[]
These signals are level sensitive. It means the interrupt is raised until it is cleared.
@ -126,4 +210,8 @@ The exception code field (`mcause` CSR) depends on the interrupt source.
Wait for Interrupt
^^^^^^^^^^^^^^^^^^
* CVA6 implementation: `WFI` stalls the core. The instruction is not available in U-mode (raise illegal instruction exception). Such exception is also raised when `TW=1` in `mstatus`.
* CVA6 implementation: `WFI` stalls the core until an interrupt occurs.
ifeval::[{RVU} == true]
The instruction is not available in U-mode (raise illegal instruction exception).
Such exception is also raised when `TW=1` in `mstatus`.
endif::[]

7
docs/design/design-manual/source/architecture.adoc
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@ -14,13 +14,13 @@ Architecture and Modules
The {ohg-config} is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.
For ASIC synthesis, the whole design is completely synchronous and uses positive-edge triggered flip-flops. The core occupies an area of about 80 kGE. The clock frequency can be more than 1GHz depending of technology.
For ASIC synthesis, the whole design is completely synchronous and uses positive-edge triggered flip-flops. The core occupies an area of about 80 kGE. The clock frequency can be more than 1 GHz depending of technology.
The {ohg-config} subsystem is composed of 8 modules.
image:subsystems.png[{ohg-config} modules]
Connections between modules are illustrated in the following block diagram. FRONTEND, DECODE, ISSUE, EXECUTE, COMMIT and CONTROLLER are part of the pipeline. And CACHES implements the instruction and data caches and CSRFILE contains registers.
Connections between modules are illustrated in the following block diagram. FRONTEND, DECODE, ISSUE, EXECUTE, COMMIT and CONTROLLER are part of the pipeline. The CSRFILE contains the registers.
image:{ohg-config}_subsystems.png[{ohg-config} pipeline and modules]
@ -31,4 +31,7 @@ include::cva6_execute.adoc[]
include::cva6_commit_stage.adoc[]
include::cva6_controller.adoc[]
include::cva6_csr_regfile.adoc[]
ifeval::[{PipelineOnly} == false]
include::cva6_caches.adoc[]
endif::[]

4
docs/design/design-manual/source/cva6_commit_stage.adoc
View file

@ -29,9 +29,11 @@ exception) or happen in commit stage, coming from the CSR_REGFILE or
from an interrupt. Exceptions are precise: they are considered during
the commit only and associated with the related instruction.
////
The module is connected to:
* TO BE COMPLETED
////
include::port_commit_stage.adoc[]
@ -39,4 +41,4 @@ include::port_commit_stage.adoc[]
Functionality
^^^^^^^^^^^^^
TO BE COMPLETED
// TO BE COMPLETED

4
docs/design/design-manual/source/cva6_controller.adoc
View file

@ -16,11 +16,13 @@ CONTROLLER Module
Description
^^^^^^^^^^^
////
The CONTROLLER module implements ... TO BE COMPLETED
The module is connected to:
* TO BE COMPLETED
////
include::port_controller.adoc[]
@ -28,4 +30,4 @@ include::port_controller.adoc[]
Functionality
^^^^^^^^^^^^^
TO BE COMPLETED
// TO BE COMPLETED

4
docs/design/design-manual/source/cva6_csr_regfile.adoc
View file

@ -16,11 +16,13 @@ CSR_REGFILE Module
Description
^^^^^^^^^^^
////
The CSR_REGFILE module implements ... TO BE COMPLETED
The module is connected to:
* TO BE COMPLETED
////
include::port_csr_regfile.adoc[]
@ -28,4 +30,4 @@ include::port_csr_regfile.adoc[]
Functionality
^^^^^^^^^^^^^
TO BE COMPLETED
// TO BE COMPLETED

6
docs/design/design-manual/source/cva6_execute.adoc
View file

@ -13,13 +13,13 @@ It encapsulates the following functional units: ALU, Branch Unit, CSR buffer, Mu
The module is connected to:
* ID_STAGE module provides scoreboard entry.
*
*
[[ex_stage-functionality]]
Functionality
^^^^^^^^^^^^^
TO BE COMPLETED
// TO BE COMPLETED
[[ex_stage-submodules]]
Submodules
@ -145,6 +145,6 @@ include::port_lsu_bypass.adoc[]
CVXIF_fu
++++++++
TO BE COMPLETED
// TO BE COMPLETED
include::port_cvxif_fu.adoc[]

16
docs/design/design-manual/source/cva6_frontend.adoc
View file

@ -17,7 +17,7 @@ FRONTEND Module
Description
^^^^^^^^^^^
The FRONTEND module implements two first stages of the cva6 pipeline,
The FRONTEND module implements two first stages of the CVA6 pipeline,
PC gen and Fetch stages.
PC gen stage is responsible for generating the next program counter.
@ -142,14 +142,14 @@ Incomplete instruction is stored in instr_realign submodule until its second hal
Below is a table that explains how the instr_realign works:
* _C : compressed instruction_
* _I : not compressed instruction_
* _C: compressed instruction_
* _I: not compressed instruction_
* _UI: Incomplete instruction stored in the instr_realign_
ifeval::[{Superscalar} == true]
|==========================================================
|*Address[2:1]* |*Incomplete Access* |*64-48* |*48-32* |*32-16* |*16-0*
|*Address[2:1]* |*Incomplete Access* |*64-48* |*48-32* |*32-16* |*16-0*
.13+^.^|0
.5+^.^|1
@ -217,7 +217,7 @@ endif::[]
ifeval::[{Superscalar} == false]
|==========================================================
|*Address[2:1]* |*Incomplete Access* |*32-16* |*16-0*
|*Address[2:1]* |*Incomplete Access* |*32-16* |*16-0*
.5+^.^|0
.3+^.^|0
@ -272,7 +272,7 @@ Instr_scan submodule
As compressed extension is enabled, {instr-per-fetch} instr_scan are instantiated to handle up to {instr-per-fetch} instructions per cycle.
Each instr_scan submodule pre-decodes the fetched instructions coming from the instr_realign module, also calculate the immediate, instructions could be compressed or not.
The instr_scan submodule is a flox controler which provides the intruction type: branch, jump, return, jalr, imm, call or others.
The instr_scan submodule is a flow controller which provides the intruction type: branch, jump, return, jalr, imm, call or others.
These outputs are used by the branch prediction feature.
include::port_instr_scan.adoc[]
@ -285,8 +285,8 @@ BHT (Branch History Table) submodule
The BHT is implemented as a memory which is composed of {BHTEntries} entries.
The BHT is a two-dimensional table:
* The first dimension represents the access address, with a length equal to `{BHTEntries} / {instr-per-fetch}`.
* The second dimension represents the row index, with a length equal to `{instr-per-fetch}`.
* The first dimension represents the access address, with a length equal to `{BHTEntries} / {instr-per-fetch}`.
* The second dimension represents the row index, with a length equal to `{instr-per-fetch}`.
In the case of branch prediction, the BHT uses only part of the virtual address to get the value of the saturation counter.
In the case of a valid misprediction, the BHT uses only part of the misprediction address to access the BHT table and update the saturation counter.

2
docs/design/design-manual/source/design.adoc
View file

@ -21,7 +21,7 @@ ifeval::[{SuperscalarEn} == false]
:ifetch-len: 32
:instr-per-fetch: 2
:issue-width: 1
:commit-width: {NrCommmitPorts}
:commit-width: {NrCommitPorts}
endif::[]
:SpeculativeSb: {SuperscalarEn}

7
docs/design/design-manual/source/functionality.adoc
View file

@ -15,5 +15,12 @@ Functionality
include::instructions.adoc[]
include::traps.adoc[]
include::CSRs.adoc[]
ifeval::[{PipelineOnly} == true]
include::OBI.adoc[]
endif::[]
ifeval::[{PipelineOnly} == false]
include::AXI.adoc[]
endif::[]
include::CVXIF.adoc[]

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40
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@ -1,5 +1,5 @@
////
Copyright 2022 Thales DIS design services SAS
Copyright 2025 Thales DIS France SAS
Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
@ -55,28 +55,32 @@ specifications.
* *[CVA6req]* “CVA6 requirement specification”,
https://github.com/openhwgroup/cva6/blob/master/docs/specifications/cva6_requirement_specification.rst,
HASH#767c465.
* *[RVunpriv]* “The RISC-V Instruction Set Manual, Volume I: User-Level
ISA, Document Version 20191213”, Editors Andrew Waterman and Krste
Asanović, RISC-V Foundation, December 13, 2019.
* *[RVpriv]* “The RISC-V Instruction Set Manual, Volume II: Privileged
Architecture, Document Version 20211203”, Editors Andrew Waterman, Krste
Asanović and John Hauser, RISC-V Foundation, December 4, 2021.
* *[RVunpriv]* “The RISC-V Instruction Set Manual for CV32A60X, Volume I: User-Level
ISA”,
https://docs.openhwgroup.org/projects/cva6-user-manual/07_cv32a60x/riscv/unpriv.html.
* *[RVpriv]* “The RISC-V Instruction Set Manual for CV32A60X, Volume II: Privileged
Architecture”,
https://docs.openhwgroup.org/projects/cva6-user-manual/07_cv32a60x/riscv/priv.html.
ifeval::[{DebugEn} == true]
* *[RVdbg]* “RISC-V External Debug Support, Document Version 0.13.2”,
Editors Tim Newsome and Megan Wachs, RISC-V Foundation, March 22, 2019.
endif::[]
* *[RVcompat]* “RISC-V Architectural Compatibility Test Framework”,
https://github.com/riscv-non-isa/riscv-arch-test.
ifeval::[{PipelineOnly} == false]
* *[AXI]* AXI Specification,
https://developer.arm.com/documentation/ihi0022/hc.
* *[CV-X-IF]* Placeholder for the CV-X-IF coprocessor interface
currently prepared at OpenHW Group; current version in
https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/.
* *[OpenPiton]* “OpenPiton Microarchitecture Specification”, Princeton
University,
https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf.
endif::[]
ifeval::[{PipelineOnly} == true]
* *[OBI]* OBI Specification v1.6.0,
https://github.com/openhwgroup/obi/blob/072d9173c1f2d79471d6f2a10eae59ee387d4c6f/OBI-v1.6.0.pdf
endif::[]
* *[CV-X-IF]* Core-V eXtension interface (CV-X-IF) v1.0.0,
https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en/v1.0.0/.
{ohg-config} is a standards-compliant {XLEN}-bit processor fully compliant with
RISC-V specifications: [RVunpriv], [RVpriv] and [RVdbg] and passes
[RVcompat] compatibility tests, as requested by [GEN-10] in [CVA6req].
above specifications. In the meanwhile, the conformity of {ohg-config} versus
[RVcompat] has not been tested.
[[documentation-framework]]
Documentation framework
@ -89,7 +93,7 @@ to as Common Criteria or CC) is an international standard (ISO/IEC
Description of the framework:
* Processor is split into module corresponding to the main modules of
* Processor is split into modules corresponding to the main modules of
the design
* Modules can contain several modules
* Each module is described in a chapter, which contains the following
@ -113,8 +117,10 @@ Contributors
[verse]
--
Jean-Roch Coulon - Thales
André Sintzoff - Thales
Yannick Casamatta - Thales
Guillaume Chauvon - Thales
Ayoub Jalali (mailto:ayoub.jalali@external.thalesgroup.com[ayoub.jalali@external.thalesgroup.com])
Alae Eddine Ezzejjari (mailto:alae-eddine.ez-zejjari@external.thalesgroup.com[alae-eddine.ez-zejjari@external.thalesgroup.com])
--
*[TO BE COMPLETED]*

11
docs/design/design-manual/source/subsystem.adoc
View file

@ -16,8 +16,8 @@ Subsystem
Global functionality
~~~~~~~~~~~~~~~~~~~~
The CVA6 is a subsystem composed of the modules and protocol interfaces
as illustrated The processor is a Harvard-based modern architecture.
The {ohg-config} is a subsystem composed of the modules and protocol interfaces
as illustrated. The processor is a Harvard-based modern architecture.
Instructions are issued in-order through the DECODE stage and executed
out-of-order but committed in-order. The processor is Single issue, that
means that at maximum one instruction per cycle can be issued to the
@ -31,11 +31,10 @@ Commit stage. At least 6 cycles are needed to execute one instruction.
Connection with other sub-systems
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The submodule is connected to :
The submodule is connected to:
* NOC interconnect provides memory content
* OBI interconnect gives access to memory content
* COPROCESSOR connects through CV-X-IF coprocessor interface protocol
* TRACER provides support for verification
* TRAP provides traps inputs
[[parameter-configuration]]
@ -48,4 +47,4 @@ include::parameters.adoc[]
IO ports
~~~~~~~~
include::port_cva6.adoc[]
include::port_cva6_pipeline.adoc[]

25
docs/scripts/define_blacklist.py
View file

@ -29,6 +29,27 @@ def define_blacklist(parameters):
black_list["dcache_cmo_req_i"] = ["For any HW configuration", "0"]
black_list["dcache_cmo_resp_o"] = ["For any HW configuration", "open"]
param = "PipelineOnly"
paramvalue = parameters[param].value
if paramvalue == True:
black_list["icache_enable_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["icache_flush_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["dcache_enable_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["dcache_flush_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["dcache_flush_ack_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["fetch_req_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["fetch_rsp_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["load_req_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["load_rsp_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["dcache_wbuffer_empty_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["dcache_wbuffer_not_ni_i"] = [f"As {param} = {paramvalue}", "0"]
param = "RVZCMT"
paramvalue = parameters[param].value
if paramvalue == False:
black_list["obi_zcmt_req_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["obi_zcmt_rsp_i"] = [f"As {param} = {paramvalue}", "0"]
param = "IsRVFI"
paramvalue = "0"
if paramvalue == "0":
@ -165,6 +186,8 @@ def define_blacklist(parameters):
black_list["amo_resp_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["amo_valid_commit_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["amo_valid_commit_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["obi_amo_req_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["obi_amo_rsp_i"] = [f"As {param} = {paramvalue}", "0"]
param = "PRIV"
paramvalue = "MachineOnly"
@ -199,5 +222,7 @@ def define_blacklist(parameters):
black_list["flush_tlb_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["flush_tlb_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["dtlb_ppn_i"] = [f"As {param} = {paramvalue}", "0"]
black_list["obi_mmu_ptw_req_o"] = [f"As {param} = {paramvalue}", "0"]
black_list["obi_mmu_ptw_rsp_i"] = [f"As {param} = {paramvalue}", "0"]
return black_list

5
docs/scripts/spec_builder.py
View file

@ -106,7 +106,7 @@ def print_to_rst(pathout, target, module, ports, comments):
fout.write("\n")
if len(comments) != 0:
fout.write(
f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n"
f"Due to {target.upper()} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n"
)
fout.write("\n")
for comment in comments:
@ -138,7 +138,7 @@ def print_to_adoc(pathout, target, module, ports, comments):
if len(comments) != 0:
fout.write(
f"Due to {target} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n\n"
f"Due to {target.upper()} configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below\n\n"
)
for comment in comments:
fout.write(f"{comment[0]},::\n* {comment[1]}\n")
@ -189,6 +189,7 @@ def main():
if args.gen_ports_folder is not None:
file = []
file.append("../core/cva6.sv")
file.append("../core/cva6_pipeline.sv")
file.append("../core/frontend/frontend.sv")
file.append("../core/frontend/bht.sv")
file.append("../core/frontend/btb.sv")