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Add more constraints to cover corner cases in CC (#1632)

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Jalali 2023-11-15 23:59:11 +01:00 • committed by GitHub
parent 4b63f43df0
commit 0bf653a95b
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3 changed files with 65 additions and 20 deletions
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13
verif/env/corev-dv/cva6_illegal_instr.sv vendored
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@ -63,12 +63,13 @@ class cva6_illegal_instr_c extends riscv_illegal_instr;
// Invalid SYSTEM instructions
constraint system_instr_c {
if (exception == kIllegalSystemInstr) {
opcode == 7'b1110011;
func3 == 3'b000;
// ECALL/EBREAK/xRET/WFI
// Constrain the upper 12 bits to avoid ecall instruction
instr_bin[31:20] != 0;
if (!(SUPERVISOR_MODE inside supported_privileged_mode)) {
if (exception == kIllegalSystemInstr) {
opcode == 7'b1110011;
func3 == 3'b000;
// Constrain the upper 12 bits to generate SRET instruction
instr_bin[31:20] == 12'b100000010;
}
}
}

3
verif/env/corev-dv/cva6_instr_sequence.sv vendored
View file

@ -45,7 +45,8 @@ class cva6_instr_sequence_c extends riscv_instr_sequence;
bin_instr_cnt, cfg_cva6.unsupported_instr_ratio), UVM_LOW)
repeat (bin_instr_cnt) begin
`DV_CHECK_RANDOMIZE_WITH_FATAL(unsupported_instr,
unsupported_instr inside {rv64i_instr,rv64c_instr,rv64m_instr,rvfdq_instr,illegal_slli_srai,sys_instr};)
unsupported_instr inside {rv64i_instr, rv64c_instr, rv64m_instr, rvfdq_instr, illegal_slli_srai, sys_instr,
illegal_rv32zcb_instr, rv64zcb_instr, rv32vf_instr};)
str = {indent, $sformatf(".4byte 0x%s # %0s",
unsupported_instr.get_bin_str(), unsupported_instr.comment)};
idx = $urandom_range(0, instr_string_list.size());

69
verif/env/corev-dv/cva6_unsupported_instr.sv vendored
View file

@ -26,13 +26,16 @@ class cva6_unsupported_instr_c extends uvm_object;
string comment;
typedef enum bit [2:0] {
typedef enum bit [3:0] {
rv64i_instr,
rv64c_instr,
rv64m_instr,
rvfdq_instr,
sys_instr,
illegal_slli_srai
illegal_slli_srai,
rv64zcb_instr,
illegal_rv32zcb_instr,
rv32vf_instr
} illegal_ext_instr_type_e;
// Default legal opcode for RV32I instructions
@ -119,7 +122,10 @@ class cva6_unsupported_instr_c extends uvm_object;
rv64m_instr := 3,
rvfdq_instr := 3,
sys_instr := 1,
illegal_slli_srai := 1
illegal_slli_srai := 1,
rv64zcb_instr := 1,
illegal_rv32zcb_instr := 1,
rv32vf_instr :=1
};
}
@ -178,7 +184,7 @@ class cva6_unsupported_instr_c extends uvm_object;
// RV64I instructions
constraint rv64i_instr_c {
if (!RV64I inside {supported_isa}) {
if (!(RV64I inside {supported_isa})) {
if (unsupported_instr == rv64i_instr) {
compressed == 0;
opcode inside {legal_rv64i_opcode};
@ -216,7 +222,7 @@ class cva6_unsupported_instr_c extends uvm_object;
// RV64M instructions
constraint rv64m_instr_c {
if (!RV64M inside {supported_isa}) {
if (!(RV64M inside {supported_isa})) {
if (unsupported_instr == rv64m_instr) {
compressed == 0;
opcode == 7'b0111011;
@ -226,12 +232,21 @@ class cva6_unsupported_instr_c extends uvm_object;
}
}
// RV32 Vectorial FP instructions
constraint rv32vf_instr_c {
if (unsupported_instr == rv32vf_instr) {
compressed == 0;
opcode == 7'b0110011;
instr_bin[31:30] == 2'b10;
}
}
// RV64C instructions
constraint rv64c_instr_c {
if (!RV64C inside {supported_isa} ||
!RV32FC inside {supported_isa} ||
!RV32DC inside {supported_isa} ||
!RV128C inside {supported_isa}) {
if (!(RV64C inside {supported_isa}) ||
!(RV32FC inside {supported_isa}) ||
!(RV32DC inside {supported_isa}) ||
!(RV128C inside {supported_isa})) {
if (unsupported_instr == rv64c_instr) {
compressed == 1;
c_op != 2'b11;
@ -259,12 +274,40 @@ class cva6_unsupported_instr_c extends uvm_object;
}
}
// RV64Zcb instructions
constraint rv64zcb_instr_c {
if (unsupported_instr == rv64zcb_instr) {
compressed == 1;
c_op == 2'b01;
c_msb == 3'b100;
instr_bin[12:10] == 3'b111;
instr_bin[6:2] == 5'b11100;
}
}
// Illegal RV32Zcb instructions
constraint illegal_rv32zcb_instr_c {
if (unsupported_instr == illegal_rv32zcb_instr) {
compressed == 1;
c_op inside {2'b00, 2'b01};
c_msb == 3'b100;
if (c_op == 2'b00) {
!(instr_bin[12:10] inside {3'b000, 3'b001, 3'b010, 3'b011});
}
if (c_op == 2'b01) {
instr_bin[12:10] == 3'b111;
!(instr_bin[4:2] inside {3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101});
instr_bin[6:5] == 2'b11;
}
}
}
// RV32FDQ, RV64FDQ instructions
constraint rvfdq_instr_c {
if (!RV32F inside {supported_isa} ||
!RV64F inside {supported_isa} ||
!RV32D inside {supported_isa} ||
!RV64D inside {supported_isa}) {
if (!(RV32F inside {supported_isa}) ||
!(RV64F inside {supported_isa}) ||
!(RV32D inside {supported_isa}) ||
!(RV64D inside {supported_isa})) {
if (unsupported_instr == rvfdq_instr) {
compressed == 0;
opcode inside {legal_rvfdq_opcode};