mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-23 05:37:16 -04:00
Fix PLIC address map and DTS
This commit is contained in:
Florian Zaruba
parent
38341670c6
commit
0c8eb5a52e
7 changed files with 252 additions and 271 deletions
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@ -14,7 +14,7 @@
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imc";
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riscv,isa = "rv64imac";
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mmu-type = "riscv,sv39";
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clock-frequency = <50000000>;
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CPU0_intc: interrupt-controller {
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@ -46,7 +46,7 @@
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reg = <0x0 0xc000000 0x0 0x4000000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev = <53>;
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riscv,ndev = <2>;
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};
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debug-controller@0 {
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compatible = "riscv,debug-013";
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Binary file not shown.
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@ -23,168 +23,168 @@ module bootrom (
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localparam int RomSize = 216;
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const logic [RomSize-1:0][63:0] mem = {
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64'h006b,
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64'h636f6c63_00737470,
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64'h75727265_746e6900,
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64'h746e6572_61702d74,
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64'h006b_636f6c63,
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64'h00737470_75727265,
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64'h746e6900_746e6572,
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64'h61702d74_70757272,
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64'h65746e69_00766564,
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64'h6e2c7663_73697200,
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64'h79746972_6f697270,
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64'h2d78616d_2c766373,
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64'h69720073_656d616e,
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64'h2d676572_00646564,
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64'h6e657478_652d7374,
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64'h70757272_65746e69,
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64'h00766564_6e2c7663,
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64'h73697200_79746972,
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64'h6f697270_2d78616d,
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64'h00736567_6e617200,
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64'h656c646e_6168702c,
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64'h78756e69_6c007265,
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64'h6c6c6f72_746e6f63,
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64'h2d747075_72726574,
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64'h6e690073_6c6c6563,
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64'h2d747075_72726574,
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64'h6e692300_79636e65,
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64'h75716572_662d6b63,
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64'h6f6c6300_65707974,
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64'h2d756d6d_00617369,
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64'h2c766373_69720073,
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64'h656d616e_2d676572,
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64'h00646564_6e657478,
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64'h652d7374_70757272,
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64'h65746e69_00736567,
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64'h6e617200_656c646e,
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64'h6168702c_78756e69,
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64'h6c007265_6c6c6f72,
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64'h746e6f63_2d747075,
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64'h72726574_6e690073,
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64'h6c6c6563_2d747075,
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64'h72726574_6e692300,
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64'h79636e65_75716572,
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64'h662d6b63_6f6c6300,
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64'h65707974_2d756d6d,
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64'h00617369_2c766373,
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64'h69720073_75746174,
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64'h73006765_72006570,
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64'h79745f65_63697665,
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64'h64007963_6e657571,
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64'h6572662d_65736162,
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64'h656d6974_006c6564,
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64'h6f6d0065_6c626974,
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64'h61706d6f_6300736c,
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64'h6c65632d_657a6973,
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64'h2300736c_6c65632d,
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64'h73736572_64646123,
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64'h09000000_02000000,
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64'h02000000_00000030,
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64'h66697468_2c626375,
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64'h1b000000_0a000000,
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64'h03000000_00000000,
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64'h66697468_01000000,
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64'h75746174_73006765,
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64'h72006570_79745f65,
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64'h63697665_64007963,
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64'h6e657571_6572662d,
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64'h65736162_656d6974,
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64'h006c6564_6f6d0065,
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64'h6c626974_61706d6f,
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64'h6300736c_6c65632d,
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64'h657a6973_2300736c,
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64'h6c65632d_73736572,
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64'h64646123_09000000,
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64'h02000000_02000000,
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64'h80f0fa02_0c010000,
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64'h04000000_03000000,
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64'h02000000_01000000,
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64'h00000000_01010000,
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64'h0c000000_03000000,
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64'h02000000_f0000000,
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64'h04000000_03000000,
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64'h00000100_00000000,
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64'h00000010_00000000,
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64'h4b000000_10000000,
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64'h03000000_00000000,
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64'h612e3230_2e312d65,
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64'h74696c74_7261752d,
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64'h6978612c_786e6c78,
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64'h1b000000_19000000,
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64'h03000000_00000030,
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64'h30303030_30303140,
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64'h74726175_01000000,
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64'h02000000_006c6f72,
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64'h746e6f63_c8000000,
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64'h08000000_03000000,
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64'h00100000_00000000,
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64'h00000000_00000000,
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64'h4b000000_10000000,
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64'h03000000_ffff0000,
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64'h01000000_b4000000,
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64'h08000000_03000000,
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64'h00333130_2d677562,
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64'h65642c76_63736972,
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64'h1b000000_10000000,
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64'h03000000_00003040,
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64'h72656c6c_6f72746e,
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64'h6f632d67_75626564,
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64'h00000030_66697468,
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64'h2c626375_1b000000,
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64'h0a000000_03000000,
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64'h00000000_66697468,
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64'h01000000_02000000,
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64'h02000000_80f0fa02,
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64'h0c010000_04000000,
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64'h03000000_02000000,
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64'h01000000_00000000,
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64'h01010000_0c000000,
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64'h03000000_02000000,
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64'hf0000000_04000000,
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64'h03000000_00000100,
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64'h00000000_00000010,
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64'h00000000_4b000000,
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64'h10000000_03000000,
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64'h00000000_612e3230,
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64'h2e312d65_74696c74,
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64'h7261752d_6978612c,
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64'h786e6c78_1b000000,
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64'h19000000_03000000,
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64'h00000030_30303030,
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64'h30303140_74726175,
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64'h01000000_02000000,
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64'h02000000_a5000000,
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64'h04000000_03000000,
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64'h02000000_9f000000,
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64'h04000000_03000000,
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64'h35000000_e5000000,
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64'h04000000_03000000,
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64'h07000000_d2000000,
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64'h04000000_03000000,
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64'h006c6f72_746e6f63,
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64'hc8000000_08000000,
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64'h03000000_00000004,
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64'h00000000_0000000c,
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64'h03000000_00100000,
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64'h00000000_00000000,
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64'h00000000_4b000000,
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64'h10000000_03000000,
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64'h09000000_01000000,
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64'h0b000000_01000000,
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64'hb4000000_10000000,
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64'h03000000_8a000000,
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64'h00000000_03000000,
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64'h00306369_6c702c76,
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64'hffff0000_01000000,
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64'hb4000000_08000000,
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64'h03000000_00333130,
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64'h2d677562_65642c76,
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64'h63736972_1b000000,
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64'h0c000000_03000000,
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64'h01000000_79000000,
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64'h04000000_03000000,
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64'h00000000_30303030,
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64'h30306340_72656c6c,
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64'h6f72746e_6f632d74,
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64'h70757272_65746e69,
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64'h01000000_02000000,
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64'h00000c00_00000000,
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64'h00000002_00000000,
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64'h4b000000_10000000,
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64'h10000000_03000000,
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64'h00003040_72656c6c,
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64'h6f72746e_6f632d67,
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64'h75626564_01000000,
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64'h02000000_02000000,
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64'ha5000000_04000000,
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64'h03000000_02000000,
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64'h9f000000_04000000,
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64'h03000000_02000000,
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64'he5000000_04000000,
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64'h03000000_07000000,
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64'h01000000_03000000,
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64'hd2000000_04000000,
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64'h03000000_006c6f72,
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64'h746e6f63_c8000000,
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64'h08000000_03000000,
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64'h00000004_00000000,
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64'h0000000c_00000000,
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64'h4b000000_10000000,
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64'h03000000_09000000,
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64'h01000000_0b000000,
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64'h01000000_b4000000,
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64'h10000000_03000000,
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64'h00000000_30746e69,
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64'h6c632c76_63736972,
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64'h1b000000_0d000000,
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64'h03000000_00000030,
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64'h30303030_30324074,
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64'h6e696c63_01000000,
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64'had000000_00000000,
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64'h03000000_00007375,
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64'h622d656c_706d6973,
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64'h00636f73_2d657261,
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64'h622d656e_61697261,
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64'h2c687465_1b000000,
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64'h1f000000_03000000,
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64'h02000000_0f000000,
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64'h04000000_03000000,
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64'h02000000_00000000,
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64'h04000000_03000000,
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64'h00636f73_01000000,
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64'h02000000_00000002,
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64'h00000000_00000080,
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64'h00000000_4b000000,
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64'h10000000_03000000,
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64'h00007972_6f6d656d,
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64'h3f000000_07000000,
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64'h03000000_00303030,
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64'h30303030_38407972,
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64'h6f6d656d_01000000,
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64'h02000000_02000000,
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64'h02000000_01000000,
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64'ha5000000_04000000,
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64'h03000000_01000000,
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64'h9f000000_04000000,
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64'h03000000_00006374,
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64'h6e692d75_70632c76,
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64'h63736972_1b000000,
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64'h0f000000_03000000,
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64'h8a000000_00000000,
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64'h03000000_00306369,
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64'h6c702c76_63736972,
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64'h1b000000_0c000000,
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64'h03000000_01000000,
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64'h79000000_04000000,
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64'h03000000_00000000,
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64'h30303030_30306340,
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64'h72656c6c_6f72746e,
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64'h6f632d74_70757272,
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64'h65746e69_01000000,
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64'h80f0fa02_69000000,
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64'h02000000_00000c00,
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64'h00000000_00000002,
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64'h00000000_4b000000,
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64'h10000000_03000000,
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64'h07000000_01000000,
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64'h03000000_01000000,
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64'hb4000000_10000000,
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64'h03000000_00000000,
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64'h30746e69_6c632c76,
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64'h63736972_1b000000,
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64'h0d000000_03000000,
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64'h00000030_30303030,
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64'h30324074_6e696c63,
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64'h01000000_ad000000,
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64'h00000000_03000000,
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64'h00007375_622d656c,
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64'h706d6973_00636f73,
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64'h2d657261_622d656e,
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64'h61697261_2c687465,
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64'h1b000000_1f000000,
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64'h03000000_02000000,
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64'h0f000000_04000000,
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64'h03000000_02000000,
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64'h00000000_04000000,
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64'h03000000_00636f73,
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64'h01000000_02000000,
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64'h00000002_00000000,
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64'h00000080_00000000,
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64'h4b000000_10000000,
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64'h03000000_00007972,
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64'h6f6d656d_3f000000,
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64'h07000000_03000000,
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64'h00303030_30303030,
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64'h38407972_6f6d656d,
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64'h01000000_02000000,
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64'h02000000_02000000,
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64'h01000000_a5000000,
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64'h04000000_03000000,
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64'h00003933_76732c76,
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64'h63736972_60000000,
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64'h0b000000_03000000,
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64'h00636d69_34367672,
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64'h56000000_08000000,
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64'h01000000_9f000000,
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64'h04000000_03000000,
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64'h00006374_6e692d75,
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64'h70632c76_63736972,
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64'h1b000000_0f000000,
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64'h03000000_8a000000,
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64'h00000000_03000000,
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64'h01000000_79000000,
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64'h04000000_03000000,
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64'h00000000_72656c6c,
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64'h6f72746e_6f632d74,
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64'h70757272_65746e69,
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64'h01000000_80f0fa02,
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64'h69000000_04000000,
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64'h03000000_00003933,
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64'h76732c76_63736972,
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64'h60000000_0b000000,
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64'h03000000_00000000,
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64'h63616d69_34367672,
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64'h56000000_09000000,
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64'h03000000_00000076,
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64'h63736972_1b000000,
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64'h06000000_03000000,
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@ -218,11 +218,11 @@ module bootrom (
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64'h00000000_01000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'hf0040000_12010000,
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64'hf4040000_12010000,
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64'h00000000_10000000,
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64'h11000000_28000000,
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64'h28050000_38000000,
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64'h3a060000_edfe0dd0,
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64'h2c050000_38000000,
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64'h3e060000_edfe0dd0,
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64'h00000000_00000000,
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64'h00000000_00000000,
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64'h00000000_00000000,
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@ -8,41 +8,41 @@ source scripts/add_sources.tcl
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read_xdc constraints/ariane.xdc
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read_xdc constraints/genesys-2.xdc
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read_ip ariane.srcs/sources_1/ip/axi_clock_converter_0/axi_clock_converter_0.xci
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read_ip ariane.srcs/sources_1/ip/axi_dwidth_converter_0/axi_dwidth_converter_0.xci
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read_ip ariane.srcs/sources_1/ip/axi_protocol_checker_0/axi_protocol_checker_0.xci
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read_ip ariane.srcs/sources_1/ip/axi_protocol_converter_0/axi_protocol_converter_0.xci
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read_ip ariane.srcs/sources_1/ip/axi_uartlite_1/axi_uartlite_1.xci
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read_ip ariane.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
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read_ip ariane.srcs/sources_1/ip/mig_7series_0/mig_7series_0.xci
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read_ip /scratch/zarubaf/ariane/fpga/xilinx/ariane_axi_clock_converter.xci
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# read_ip ariane.srcs/sources_1/ip/axi_dwidth_converter_0/axi_dwidth_converter_0.xci
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# read_ip ariane.srcs/sources_1/ip/axi_protocol_checker_0/axi_protocol_checker_0.xci
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# read_ip ariane.srcs/sources_1/ip/axi_protocol_converter_0/axi_protocol_converter_0.xci
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# read_ip ariane.srcs/sources_1/ip/axi_uartlite_1/axi_uartlite_1.xci
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# read_ip ariane.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
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# read_ip ariane.srcs/sources_1/ip/mig_7series_0/mig_7series_0.xci
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# Synthesis
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synth_design -top ariane_xilinx -part xc7k325tffg900-2 -flatten rebuilt -verilog_define FPGA_TARGET_XILINX=1
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write_checkpoint -force $outputDir/post_synth
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report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
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report_power -file $outputDir/post_synth_power.rpt
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# synth_design -top ariane_xilinx -part xc7k325tffg900-2 -flatten rebuilt -verilog_define FPGA_TARGET_XILINX=1
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# write_checkpoint -force $outputDir/post_synth
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# report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
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# report_power -file $outputDir/post_synth_power.rpt
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# Implementation
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# # Implementation
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opt_design
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power_opt_design
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place_design
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phys_opt_design
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write_checkpoint -force $outputDir/post_place
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report_timing_summary -file $outputDir/post_place_timing_summary.rpt
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# opt_design
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# power_opt_design
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# place_design
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||||
# phys_opt_design
|
||||
# write_checkpoint -force $outputDir/post_place
|
||||
# report_timing_summary -file $outputDir/post_place_timing_summary.rpt
|
||||
|
||||
route_design
|
||||
write_checkpoint -force $outputDir/post_route
|
||||
# route_design
|
||||
# write_checkpoint -force $outputDir/post_route
|
||||
|
||||
report_timing_summary -file $outputDir/post_route_timing_summary.rpt
|
||||
report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
|
||||
report_clock_utilization -file $outputDir/clock_util.rpt
|
||||
report_utilization -file $outputDir/post_route_util.rpt
|
||||
report_power -file $outputDir/post_route_power.rpt
|
||||
report_drc -file $outputDir/post_imp_drc.rpt
|
||||
# report_timing_summary -file $outputDir/post_route_timing_summary.rpt
|
||||
# report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
|
||||
# report_clock_utilization -file $outputDir/clock_util.rpt
|
||||
# report_utilization -file $outputDir/post_route_util.rpt
|
||||
# report_power -file $outputDir/post_route_power.rpt
|
||||
# report_drc -file $outputDir/post_imp_drc.rpt
|
||||
|
||||
write_verilog -force $outputDir/ariane.v
|
||||
# write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc
|
||||
# write_verilog -force $outputDir/ariane.v
|
||||
# # write_xdc -no_fixed_only -force $outputDir/bft_impl.xdc
|
||||
|
||||
write_bitstream -force $outputDir/ariane.bit
|
||||
# write_bitstream -force $outputDir/ariane.bit
|
||||
|
|
|
|||
|
|
@ -60,8 +60,8 @@ module ariane_peripherals #(
|
|||
plic #(
|
||||
.ADDR_WIDTH ( AxiAddrWidth ),
|
||||
.DATA_WIDTH ( AxiDataWidth ),
|
||||
.ID_BITWIDTH ( 2 ), // TODO (zarubaf): Find propper width
|
||||
.PARAMETER_BITWIDTH ( 2 ), // TODO (zarubaf): Find propper width
|
||||
.ID_BITWIDTH ( 3 ), // TODO (zarubaf): Find propper width
|
||||
.PARAMETER_BITWIDTH ( 3 ), // TODO (zarubaf): Find propper width
|
||||
.NUM_TARGETS ( ariane_soc::NumTargets ),
|
||||
.NUM_SOURCES ( ariane_soc::NumSources )
|
||||
) i_plic (
|
||||
|
|
|
|||
|
|
@ -82,15 +82,10 @@ module plic_interface #(
|
|||
logic [DATA_WIDTH/bpw-1:0 ] ena_bundles_d[num_gateway_bundles][NUM_TARGETS][DATA_WIDTH/8];
|
||||
logic [DATA_WIDTH/bpw-1:0 ] ena_bundles_q[num_gateway_bundles][NUM_TARGETS][DATA_WIDTH/8];
|
||||
|
||||
//debug signals (only used in the wave...)
|
||||
logic [31:0] gw_bundle;
|
||||
logic [31:0] tar;
|
||||
logic [31:0] gw;
|
||||
|
||||
//assignments
|
||||
// assignments
|
||||
assign id_of_largest_priority_d = id_of_largest_priority_i;
|
||||
|
||||
//assign addresses
|
||||
// assign addresses
|
||||
assign page_address = external_bus_io.addr[ADDR_WIDTH-1:12];
|
||||
assign page_offset = external_bus_io.addr[11:0 ];
|
||||
assign page_word_offset = external_bus_io.addr[11:$clog2(bpw) ];
|
||||
|
|
@ -99,7 +94,7 @@ module plic_interface #(
|
|||
assign write_active = (external_bus_io.valid & external_bus_io.write) ? external_bus_io.wstrb : '0;
|
||||
assign read_active = external_bus_io.valid & !external_bus_io.write;
|
||||
|
||||
//bundle signals
|
||||
// bundle signals
|
||||
for (genvar bundle = 0; bundle < num_gateway_bundles; bundle++) begin
|
||||
for (genvar ip_bit = 0; ip_bit < DATA_WIDTH; ip_bit++) begin
|
||||
if (bundle * DATA_WIDTH + ip_bit < NUM_GATEWAYS) begin
|
||||
|
|
@ -111,7 +106,7 @@ module plic_interface #(
|
|||
end
|
||||
|
||||
for (genvar bundle = 0; bundle < num_gateway_bundles; bundle++) begin
|
||||
for( genvar target = 0; target < NUM_TARGETS; target++) begin
|
||||
for (genvar target = 0; target < NUM_TARGETS; target++) begin
|
||||
for (genvar byte_in_word = 0; byte_in_word < DATA_WIDTH/8; byte_in_word++) begin
|
||||
for (genvar enable_bit = 0; enable_bit < 8; enable_bit++) begin
|
||||
assign irq_enables_o[bundle * DATA_WIDTH + enable_bit + byte_in_word * 8][target] =
|
||||
|
|
@ -121,60 +116,47 @@ module plic_interface #(
|
|||
end
|
||||
end
|
||||
|
||||
//determine the function to be performed
|
||||
// determine the function to be performed
|
||||
always_comb begin : proc_address_map
|
||||
//default values
|
||||
funct = INV;
|
||||
gw_bundle = 'z;
|
||||
tar = 'z;
|
||||
gw = 'z;
|
||||
//only alligned access is allowed:
|
||||
if(word_offset == '0) begin
|
||||
//we have now an word alligned access -> check out page offset to determine
|
||||
//what type of access this is.
|
||||
if(page_address[13:0] == 0) begin //we access the gateway priority bits
|
||||
//the page_word_offset tells us now which gateway we consider
|
||||
//in order to grant or deny access, we have to check if the gateway
|
||||
//in question really exist.
|
||||
//Gateway 0 does not exist, so return an error
|
||||
if(page_word_offset<=NUM_GATEWAYS & page_word_offset > 0) begin //the gateway in question exists
|
||||
//set the current operation to be an access to the priority registers
|
||||
// default values
|
||||
funct = INV;
|
||||
// only alligned access is allowed:
|
||||
if (word_offset == '0) begin
|
||||
// we have now an word alligned access -> check out page offset to determine
|
||||
// what type of access this is.
|
||||
if (page_address[13:0] == 0) begin // we access the gateway priority bits
|
||||
// the page_word_offset tells us now which gateway we consider
|
||||
// in order to grant or deny access, we have to check if the gateway
|
||||
// in question really exist.
|
||||
// Gateway 0 does not exist, so return an error
|
||||
if (page_word_offset <= NUM_GATEWAYS && page_word_offset > 0) begin //the gateway in question exists
|
||||
// set the current operation to be an access to the priority registers
|
||||
funct = PRI;
|
||||
//debug:
|
||||
gw = page_word_offset;
|
||||
end
|
||||
//we now access the IP Bits, read only
|
||||
end else if(page_address[13:0] == 1) begin
|
||||
//the page_word_offset tells us now, which word we have to consider,
|
||||
//the word, which includes the IP bit in question should be returned
|
||||
if(page_word_offset<num_gateway_bundles) begin
|
||||
// we now access the IP Bits, read only
|
||||
end else if (page_address[13:0] == 1) begin
|
||||
// the page_word_offset tells us now, which word we have to consider,
|
||||
// the word, which includes the IP bit in question should be returned
|
||||
if (page_word_offset<num_gateway_bundles) begin
|
||||
funct = IPA;
|
||||
//debug:
|
||||
gw_bundle = page_word_offset;
|
||||
end
|
||||
//access of the enable bits for each target
|
||||
end else if(page_address[13:9] == 0) begin
|
||||
|
||||
//the bottom part page_word_offset now tells us which gateway bundle we have to consider
|
||||
//part of the page_address and the upper part of the page_word_offset give us the target nr.
|
||||
if(page_offset[6:$clog2(bpw)] < num_gateway_bundles) begin
|
||||
if(({page_address[8:0], page_offset[11:7]} - 64) < NUM_TARGETS) begin
|
||||
// access of the enable bits for each target
|
||||
end else if (page_address[13:9] == 0) begin
|
||||
// the bottom part page_word_offset now tells us which gateway bundle we have to consider
|
||||
// part of the page_address and the upper part of the page_word_offset give us the target nr.
|
||||
if (page_offset[6:$clog2(bpw)] < num_gateway_bundles) begin
|
||||
if (({page_address[8:0], page_offset[11:7]} - 64) < NUM_TARGETS) begin
|
||||
funct = IEB;
|
||||
// debug:
|
||||
gw_bundle = page_offset[6:$clog2(bpw)];
|
||||
tar = ({page_address[8:0], page_offset[11:7]} - 64);
|
||||
end
|
||||
end
|
||||
//priority / claim / complete
|
||||
// priority / claim / complete
|
||||
end else begin
|
||||
//page address - 0h20 gives the target number
|
||||
// page address - 0h20 gives the target number
|
||||
if (page_address[13:0] - 'h200 < NUM_TARGETS) begin
|
||||
//debug:
|
||||
tar = page_address[13:0] - 'h200;
|
||||
//check lowest bit of the page_word_offset to get the exact function
|
||||
if(page_word_offset == 0) begin
|
||||
// check lowest bit of the page_word_offset to get the exact function
|
||||
if (page_word_offset == 0) begin
|
||||
funct = THR;
|
||||
end else if(page_word_offset == 1) begin
|
||||
end else if (page_word_offset == 1) begin
|
||||
funct = CCP;
|
||||
end
|
||||
end
|
||||
|
|
@ -183,7 +165,7 @@ module plic_interface #(
|
|||
end
|
||||
|
||||
always_comb begin : proc_read_write
|
||||
//defalt values
|
||||
// defalt values
|
||||
external_bus_io.rdata = 0;
|
||||
external_bus_io.error = 0;
|
||||
external_bus_io.ready = 0;
|
||||
|
|
@ -199,40 +181,40 @@ module plic_interface #(
|
|||
ena_bundles_d = ena_bundles_q;
|
||||
thresholds_d = thresholds_q;
|
||||
|
||||
case(funct)
|
||||
PRI : begin
|
||||
//read case
|
||||
if(read_active != 0) begin
|
||||
case (funct)
|
||||
PRI: begin
|
||||
// read case
|
||||
if (read_active != 0) begin
|
||||
external_bus_io.rdata = priorities_q[page_word_offset-1];
|
||||
external_bus_io.ready = 1;
|
||||
//write case
|
||||
end else if(write_active[0] == 1) begin
|
||||
// write case
|
||||
end else if (write_active[0] == 1) begin
|
||||
priorities_d[page_word_offset-1] = external_bus_io.wdata[PARAMETER_BITWIDTH-1:0];
|
||||
external_bus_io.ready = 1;
|
||||
end
|
||||
end
|
||||
|
||||
IPA : begin
|
||||
//read case
|
||||
if(read_active != 0) begin
|
||||
IPA: begin
|
||||
// read case
|
||||
if (read_active != 0) begin
|
||||
external_bus_io.rdata = irq_pending_bundle[page_word_offset];
|
||||
external_bus_io.ready = 1;
|
||||
//write case
|
||||
// write case
|
||||
end else if (write_active != 0) begin
|
||||
external_bus_io.error = 1; //not allowed
|
||||
end
|
||||
end
|
||||
|
||||
IEB : begin
|
||||
//read case
|
||||
if(read_active != 0) begin
|
||||
for(integer byte_in_word=0; byte_in_word<DATA_WIDTH/8; byte_in_word++) begin
|
||||
IEB: begin
|
||||
// read case
|
||||
if (read_active != 0) begin
|
||||
for (integer byte_in_word = 0; byte_in_word < DATA_WIDTH/8; byte_in_word++) begin
|
||||
external_bus_io.rdata[8*(byte_in_word) +: 8] = ena_bundles_q[page_offset[6:$clog2(bpw)]][({page_address[8:0], page_offset[11:7]} - 64)][byte_in_word];
|
||||
end
|
||||
external_bus_io.ready = 1;
|
||||
//write case
|
||||
// write case
|
||||
end else if(write_active != 0) begin
|
||||
for(integer byte_in_word=0; byte_in_word<DATA_WIDTH/8; byte_in_word++) begin
|
||||
for (integer byte_in_word=0; byte_in_word<DATA_WIDTH/8; byte_in_word++) begin
|
||||
if(write_active[byte_in_word]) begin
|
||||
ena_bundles_d[page_offset[6:$clog2(bpw)]][({page_address[8:0], page_offset[11:7]} - 64)][byte_in_word] = external_bus_io.wdata[8*(byte_in_word) +: 8];
|
||||
end
|
||||
|
|
@ -241,26 +223,26 @@ module plic_interface #(
|
|||
end
|
||||
end
|
||||
|
||||
THR : begin
|
||||
//read case
|
||||
if(read_active != 0) begin
|
||||
THR: begin
|
||||
// read case
|
||||
if (read_active != 0) begin
|
||||
external_bus_io.rdata[PARAMETER_BITWIDTH-1:0] = thresholds_q[(page_address[13:0] - 'h200)];
|
||||
external_bus_io.ready = 1;
|
||||
//write case
|
||||
end else if(write_active != 0) begin
|
||||
// write case
|
||||
end else if (write_active != 0) begin
|
||||
thresholds_d[(page_address[13:0] - 'h200)] = external_bus_io.wdata[PARAMETER_BITWIDTH-1:0];
|
||||
external_bus_io.ready = 1;
|
||||
end
|
||||
end
|
||||
|
||||
CCP : begin
|
||||
//read case
|
||||
if(read_active != 0) begin
|
||||
CCP: begin
|
||||
// read case
|
||||
if (read_active != 0) begin
|
||||
target_irq_claims_o[(page_address[13:0] - 'h200)] = 1;
|
||||
external_bus_io.rdata[ID_BITWIDTH-1:0] = id_of_largest_priority_q[(page_address[13:0] - 'h200)];
|
||||
external_bus_io.ready = 1;
|
||||
//write case
|
||||
end else if(write_active != 0) begin
|
||||
// write case
|
||||
end else if (write_active != 0) begin
|
||||
target_irq_completes_o[(page_address[13:0] - 'h200)] = 1;
|
||||
target_irq_completes_id_o[(page_address[13:0] - 'h200)] = external_bus_io.wdata[ID_BITWIDTH-1:0];
|
||||
external_bus_io.ready = 1;
|
||||
|
|
@ -275,9 +257,9 @@ module plic_interface #(
|
|||
endcase // funct
|
||||
end
|
||||
|
||||
//store data in flip flops
|
||||
// store data in flip flops
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_update_ff
|
||||
if (~rst_ni) begin //set all registers to 0
|
||||
if (~rst_ni) begin // set all registers to 0
|
||||
for (integer gateway = 0; gateway < NUM_GATEWAYS; gateway++)
|
||||
priorities_q[gateway] <= 0;
|
||||
|
||||
|
|
@ -305,16 +287,16 @@ module plic_interface #(
|
|||
// pragma translate_off
|
||||
`ifndef VERILATOR
|
||||
initial begin
|
||||
assert((ADDR_WIDTH==32) | (ADDR_WIDTH==64)) else $error("Address width has to bei either 32 or 64 bit");
|
||||
assert((DATA_WIDTH==32) | (DATA_WIDTH==64)) else $error("Data width has to bei either 32 or 64 bit");
|
||||
assert(ID_BITWIDTH>0) else $error("ID_BITWIDTH has to be larger than 1");
|
||||
assert(ID_BITWIDTH<10) else $error("ID_BITWIDTH has to be smaller than 10");
|
||||
assert(PARAMETER_BITWIDTH>0) else $error("PARAMETER_BITWIDTH has to be larger than 1");
|
||||
assert(PARAMETER_BITWIDTH<8) else $error("PARAMETER_BITWIDTH has to be smaller than 8");
|
||||
assert(NUM_GATEWAYS>0) else $error("Num od Gateways has to be larger than 1");
|
||||
assert(NUM_GATEWAYS<512) else $error("Num of Gateways has to be smaller than 512");
|
||||
assert(NUM_TARGETS>0) else $error("Num Target slices has to be larger than 1");
|
||||
assert(NUM_TARGETS<15872) else $error("Num target slices has to be smaller than 15872");
|
||||
assert ((ADDR_WIDTH==32) | (ADDR_WIDTH==64)) else $error("Address width has to bei either 32 or 64 bit");
|
||||
assert ((DATA_WIDTH==32) | (DATA_WIDTH==64)) else $error("Data width has to bei either 32 or 64 bit");
|
||||
assert (ID_BITWIDTH>0) else $error("ID_BITWIDTH has to be larger than 1");
|
||||
assert (ID_BITWIDTH<10) else $error("ID_BITWIDTH has to be smaller than 10");
|
||||
assert (PARAMETER_BITWIDTH>0) else $error("PARAMETER_BITWIDTH has to be larger than 1");
|
||||
assert (PARAMETER_BITWIDTH<8) else $error("PARAMETER_BITWIDTH has to be smaller than 8");
|
||||
assert (NUM_GATEWAYS>0) else $error("Num od Gateways has to be larger than 1");
|
||||
assert (NUM_GATEWAYS<512) else $error("Num of Gateways has to be smaller than 512");
|
||||
assert (NUM_TARGETS>0) else $error("Num Target slices has to be larger than 1");
|
||||
assert (NUM_TARGETS<15872) else $error("Num target slices has to be smaller than 15872");
|
||||
end
|
||||
`endif
|
||||
// pragma translate_on
|
||||
|
|
|
|||
|
|
@ -37,8 +37,7 @@ package ariane_soc;
|
|||
localparam logic[63:0] DebugLength = 64'h1000;
|
||||
localparam logic[63:0] ROMLength = 64'h1000;
|
||||
localparam logic[63:0] CLINTLength = 64'hC0000;
|
||||
// TODO(zarubaf): Put PLIC back 0x4000000
|
||||
localparam logic[63:0] PLICLength = 64'h40_0000;
|
||||
localparam logic[63:0] PLICLength = 64'h3FF_FFFF;
|
||||
localparam logic[63:0] UARTLength = 64'h10000;
|
||||
localparam logic[63:0] DRAMLength = 64'h4000000;
|
||||
endpackage
|
||||
Loading…
Add table
Add a link
Reference in a new issue