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Add support for VCU118

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This commit is contained in:
Florian Zaruba 2018-11-12 16:56:06 +01:00
parent fbe2c29464
commit 0ce36534e8
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GPG key ID: E742FFE8EC38A792
18 changed files with 2987 additions and 318 deletions
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2
bootrom/ariane.dts
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@ -31,7 +31,7 @@
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x2000000>;
reg = <0x0 0x80000000 0x0 0x1800000>;
};
soc {
#address-cells = <2>;

2
bootrom/bootrom.h
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@ -180,7 +180,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x00000000,
0x00000080,
0x00000000,
0x00000002,
0x00008001,
0x02000000,
0x01000000,
0x00636f73,

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bootrom/bootrom.img
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2
bootrom/bootrom.sv
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@ -118,7 +118,7 @@ module bootrom (
64'h00000000_04000000,
64'h03000000_00636f73,
64'h01000000_02000000,
64'h00000002_00000000,
64'h00008001_00000000,
64'h00000080_00000000,
64'h5b000000_10000000,
64'h03000000_00007972,

2
fpga/ariane.cfg
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@ -1,4 +1,4 @@
adapter_khz 1000
adapter_khz 100
interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"

1990
fpga/constraints/vcu118.xdc Normal file
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File diff suppressed because it is too large Load diff

1172
fpga/src/ariane_xilinx.sv
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2
fpga/src/axi_slice

@ -1 +1 @@
Subproject commit 34338f7faf7de7787585826c1ad99aed51ee3ef5
Subproject commit aae8ca49dcfbfa8e44e1938a2e4a768db83006cb

2
fpga/src/bootrom/ariane.dts
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@ -31,7 +31,7 @@
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x2000000>;
reg = <0x0 0x80000000 0x0 0x1800000>;
};
L26: soc {
#address-cells = <2>;

8
fpga/src/bootrom/bootrom.S
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@ -3,14 +3,6 @@
.section .text.start, "ax", @progbits
.globl _start
_start:
li t0, (DRAM_BASE + 32 * 1024 * 1024)
li t1, DRAM_BASE
2:
sd x0, 0(t1)
addi t1, t1, 8
bne t1, t0, 2b
fence
fence.i
li s0, DRAM_BASE
csrr a0, mhartid
la a1, _dtb

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fpga/src/bootrom/bootrom.elf
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30
fpga/src/bootrom/bootrom.h
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@ -3,20 +3,20 @@
const int reset_vec_size = 448;
uint32_t reset_vec[reset_vec_size] = {
0x0410029b,
0x01929293,
0x0010031b,
0x01f31313,
0x00033023,
0x1de30321,
0x000ffe53,
0x100f0ff0,
0x041b0000,
0x14130010,
0x257301f4,
0x0597f140,
0x85930000,
0x84020525,
0x0010041b,
0x01f41413,
0xf1402573,
0x00000597,
0x07458593,
0x00008402,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xf1402573,
@ -180,7 +180,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x00000000,
0x00000080,
0x00000000,
0x00000002,
0x00008001,
0x02000000,
0x01000000,
0x00636f73,

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fpga/src/bootrom/bootrom.img
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16
fpga/src/bootrom/bootrom.sv
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@ -158,7 +158,7 @@ module bootrom (
64'h00000000_04000000,
64'h03000000_00636f73,
64'h01000000_02000000,
64'h00000002_00000000,
64'h00008001_00000000,
64'h00000080_00000000,
64'h5b000000_10000000,
64'h03000000_00007972,
@ -240,13 +240,13 @@ module bootrom (
64'h10500073_03c58593,
64'h00000597_f1402573,
64'h00000000_00000000,
64'h84020525_85930000,
64'h0597f140_257301f4,
64'h14130010_041b0000,
64'h100f0ff0_000ffe53,
64'h1de30321_00033023,
64'h01f31313_0010031b,
64'h01929293_0410029b
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00008402_07458593,
64'h00000597_f1402573,
64'h01f41413_0010041b
};
logic [$clog2(RomSize)-1:0] addr_q;

15
fpga/src/vcu118.svh Normal file
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@ -0,0 +1,15 @@
// Copyright 2018 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
// Description: Set global FPGA degines
// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
`define VCU118
`define FPGA_TARGET_XILINX

6
src/clint/clint.sv
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@ -60,12 +60,14 @@ module clint #(
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( AXI_ID_WIDTH )
) axi_lite_interface_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.slave ( slave ),
.address_o ( address ),
.en_o ( en ),
.we_o ( we ),
.data_i ( rdata ),
.data_o ( wdata ),
.*
.data_o ( wdata )
);
// -----------------------------

40
tb/ariane_soc_pkg.sv
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@ -12,11 +12,20 @@
// Description: Contains SoC information as constants
package ariane_soc;
localparam NB_PERIPHERALS = 7;
localparam NumTargets = 2;
localparam NumSources = 2;
typedef enum int unsigned {
`ifdef INCL_SRAM
DRAM = 0,
SRAM = 1,
SPI = 2,
UART = 3,
PLIC = 4,
CLINT = 5,
ROM = 6,
Debug = 7
`else
DRAM = 0,
SPI = 1,
UART = 2,
@ -24,8 +33,22 @@ package ariane_soc;
CLINT = 4,
ROM = 5,
Debug = 6
`endif
} axi_slaves_t;
localparam NB_PERIPHERALS = Debug + 1;
localparam logic[63:0] DebugLength = 64'h1000;
localparam logic[63:0] ROMLength = 64'h1000;
localparam logic[63:0] CLINTLength = 64'hC0000;
localparam logic[63:0] PLICLength = 64'h3FF_FFFF;
localparam logic[63:0] UARTLength = 64'h10000;
localparam logic[63:0] SPILength = 64'h1000;
localparam logic[63:0] SRAMLength = 64'h1800000; // 24 MByte of SRAM
localparam logic[63:0] DRAMLength = 64'h80000000; // 2 GByte of DDR
// Instantiate AXI protocol checkers
localparam bit GenProtocolChecker = 1'b0;
typedef enum logic [63:0] {
DebugBase = 64'h0000_0000,
ROMBase = 64'h0001_0000,
@ -33,14 +56,13 @@ package ariane_soc;
PLICBase = 64'h0C00_0000,
UARTBase = 64'h1000_0000,
SPIBase = 64'h2000_0000,
`ifdef INCL_SRAM
// let the memory appear contigouse
SRAMBase = 64'h8000_0000,
DRAMBase = 64'h8000_0000 + SRAMLength
`else
DRAMBase = 64'h8000_0000
`endif
} soc_bus_start_t;
localparam logic[63:0] DebugLength = 64'h1000;
localparam logic[63:0] ROMLength = 64'h1000;
localparam logic[63:0] CLINTLength = 64'hC0000;
localparam logic[63:0] PLICLength = 64'h3FF_FFFF;
localparam logic[63:0] UARTLength = 64'h10000;
localparam logic[63:0] SPILength = 64'h1000;
localparam logic[63:0] DRAMLength = 64'h8000000;
endpackage
endpackage

16
tb/ariane_testharness.sv
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@ -406,14 +406,16 @@ module ariane_testharness #(
// ---------------
// AXI Xbar
// ---------------
axi_node_intf_wrap #(
axi_node_wrap_with_slices #(
// three ports from Ariane (instruction, data and bypass)
.NB_SLAVE ( NB_SLAVE ),
.NB_MASTER ( ariane_soc::NB_PERIPHERALS ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_ID_WIDTH ( AXI_ID_WIDTH )
.NB_SLAVE ( NB_SLAVE ),
.NB_MASTER ( ariane_soc::NB_PERIPHERALS ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_ID_WIDTH ( AXI_ID_WIDTH ),
.MASTER_SLICE_DEPTH ( 2 ),
.SLAVE_SLICE_DEPTH ( 2 )
) i_axi_xbar (
.clk ( clk_i ),
.rst_n ( ndmreset_n ),