move cache-specific files to separate folder

Makefile

@@ -19,11 +19,11 @@ verilator      ?= verilator
 target-options ?=
 # Sources
 # Package files -> compile first
-ariane_pkg := include/riscv_pkg.sv     \
-              src/debug/dm_pkg.sv      \
-              include/ariane_pkg.sv    \
-              include/std_cache_pkg.sv \
-              include/axi_if.sv
+ariane_pkg := include/riscv_pkg.sv       \
+              src/debug/dm_pkg.sv        \
+              include/ariane_pkg.sv      \
+              include/std_cache_pkg.sv   \
+			  include/axi_if.sv
 
 # utility modules
 util := $(wildcard src/util/*.svh)         \
@@ -40,7 +40,8 @@ dpi := $(patsubst tb/dpi/%.cc,work/%.o,$(wildcard tb/dpi/*.cc))
 dpi_hdr := $(wildcard tb/dpi/*.h)
 # this list contains the standalone components
 src :=  $(filter-out src/ariane_regfile.sv, $(wildcard src/*.sv))      \
-        $(wildcard bootrom/*.sv)                                       \
+        $(wildcard src/cache_subsystem/*.sv)                           \
+		$(wildcard bootrom/*.sv)                                       \
         $(wildcard src/axi_slice/*.sv)                                 \
         $(wildcard src/clint/*.sv)                                     \
         $(wildcard src/axi_node/*.sv)                                  \

src/cache_subsystem/std_cache_subsystem.sv

@@ -45,7 +45,7 @@ module std_cache_subsystem #(
    input  logic                           dcache_flush_i,         // high until acknowledged
    output logic                           dcache_flush_ack_o,     // send a single cycle acknowledge signal when the cache is flushed
    output logic                           dcache_miss_o,          // we missed on a ld/st
-   // AMO interface
+   // AMO interface (not functional yet)
    input  logic                           dcache_amo_commit_i,    // commit atomic memory operation
    output logic                           dcache_amo_valid_o,     // we have a valid AMO result
    output logic [63:0]                    dcache_amo_result_o,    // result of atomic memory operation
@@ -61,7 +61,7 @@ module std_cache_subsystem #(
 );
 
 
-   icache #(
+   std_icache #(
    ) i_icache (
       .clk_i             ( clk_i                 ),
       .rst_ni            ( rst_ni                ),
@@ -80,7 +80,7 @@ module std_cache_subsystem #(
    // Port 0: PTW
    // Port 1: Load Unit
    // Port 2: Store Unit
-   nbdcache #(
+   std_nbdcache #(
       .CACHE_START_ADDR ( CACHE_START_ADDR )
    ) i_nbdcache (
       .clk_i              ( clk_i                  ),

src/cache_subsystem/std_icache.sv

@@ -16,7 +16,7 @@
 import ariane_pkg::*;
 import std_cache_pkg::*;
 
-module icache  #(
+module std_icache  #(
 )(
     input  logic                     clk_i,
     input  logic                     rst_ni,

src/cache_subsystem/std_nbdcache.sv

@@ -15,7 +15,7 @@
 import ariane_pkg::*;
 import std_cache_pkg::*;
 
-module nbdcache #(
+module std_nbdcache #(
         parameter logic [63:0] CACHE_START_ADDR = 64'h4000_0000
 )(
     input  logic                           clk_i,       // Clock