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munailwaqar
Munail Waqar
parent
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commit
0d44909e17
4 changed files with 34 additions and 7 deletions
15
core/alu.sv
15
core/alu.sv
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@ -309,23 +309,32 @@ module alu
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assign unzip_gen[n] = fu_data_i.operand_a[n<<1];
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assign unzip_gen[n+16] = fu_data_i.operand_a[(n<<1)+1];
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end
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// AES 32-bit final round encryption by applying rotations and the forward sbox to a single byte of rs2 based on the MSB byte of the instruction itself
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assign aes32esi_gen = (fu_data_i.operand_a ^ ({24'b0, aes_sbox_fwd((fu_data_i.operand_b >> {orig_instr_aes[5:4], 3'b000}[7:0]))} << {orig_instr_aes[5:4], 3'b000}) | ({24'b0, aes_sbox_fwd((fu_data_i.operand_b >> {orig_instr_aes[5:4], 3'b000}[7:0]))} >> (32 - {orig_instr_aes[5:4], 3'b000})));
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// AES 32-bit middle round encryption by applying rotations, forward mix-columns and the forward sbox to a single byte of rs2 based on the MSB byte of the instruction itself
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assign aes32esmi_gen = fu_data_i.operand_a ^ ((aes_mixcolumn_fwd({24'h000000, aes_sbox_fwd((fu_data_i.operand_b >> {orig_instr_aes[5:4], 3'b000}[7:0]))}) << {orig_instr_aes[5:4], 3'b000}) | (aes_mixcolumn_fwd({24'h000000, aes_sbox_fwd((fu_data_i.operand_b >> {orig_instr_aes[5:4], 3'b000}[7:0]))}) >> (32 - {orig_instr_aes[5:4], 3'b000})));
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// AES 32-bit final round decryption by applying rotations and the inverse sbox to a single byte of rs2 based on the MSB byte of the instruction itself
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assign aes32dsi_gen = (fu_data_i.operand_a ^ ({24'b0, aes_sbox_inv((fu_data_i.operand_b >> {orig_instr_aes[5:4], 3'b000}[7:0]))} << {orig_instr_aes[5:4], 3'b000}) | ({24'b0, aes_sbox_inv((fu_data_i.operand_b >> {orig_instr_aes[5:4], 3'b000}[7:0]))} >> (32 - {orig_instr_aes[5:4], 3'b000})));
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// AES 32-bit middle round decryption by applying rotations, inverse mix-columns and the inverse sbox to a single byte of rs2 based on the MSB byte of the instruction itself
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assign aes32dsmi_gen = fu_data_i.operand_a ^ ((aes_mixcolumn_inv({24'h000000, aes_sbox_inv((fu_data_i.operand_b >> {orig_instr_aes[5:4], 3'b000}[7:0]))}) << {orig_instr_aes[5:4], 3'b000}) | (aes_mixcolumn_inv({24'h000000, aes_sbox_inv((fu_data_i.operand_b >> {orig_instr_aes[5:4], 3'b000}[7:0]))}) >> (32 - {orig_instr_aes[5:4], 3'b000})));
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end
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else if (CVA6Cfg.IS_XLEN64) begin
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// Shift rows step
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// AES Shift rows forward and inverse step
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assign sr = {fu_data_i.operand_a[31:24], fu_data_i.operand_b[55:48], fu_data_i.operand_b[15:8], fu_data_i.operand_a[39:32], fu_data_i.operand_b[63:56], fu_data_i.operand_b[23:16], fu_data_i.operand_a[47:40], fu_data_i.operand_a[7:0]};
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assign sr_inv = {fu_data_i.operand_b[31:24], fu_data_i.operand_b[55:48], fu_data_i.operand_a[15:8], fu_data_i.operand_a[39:32], fu_data_i.operand_a[63:56], fu_data_i.operand_b[23:16], fu_data_i.operand_b[47:40], fu_data_i.operand_a[7:0]};
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// AES64 results
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// AES 64-bit final round encryption by applying forward shift-rows and the forward sbox to each byte
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assign aes64es_gen = {aes_sbox_fwd(sr[63:56]), aes_sbox_fwd(sr[55:48]), aes_sbox_fwd(sr[47:40]), aes_sbox_fwd(sr[39:32]), aes_sbox_fwd(sr[31:24]), aes_sbox_fwd(sr[23:16]), aes_sbox_fwd(sr[15:8]), aes_sbox_fwd(sr[7:0])};
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// AES 64-bit middle round encryption by applying forward shift-rows, forward sbox and forward mix-columns to all bytes
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assign aes64esm_gen = {aes_mixcolumn_fwd(aes64es_gen[63:32]), aes_mixcolumn_fwd(aes64es_gen[31:0])};
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// AES 64-bit final round decryption by applying inverse shift-rows and the inverse sbox to each byte
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assign aes64ds_gen = {aes_sbox_inv(sr_inv[63:56]), aes_sbox_inv(sr_inv[55:48]), aes_sbox_inv(sr_inv[47:40]), aes_sbox_inv(sr_inv[39:32]), aes_sbox_inv(sr_inv[31:24]), aes_sbox_inv(sr_inv[23:16]), aes_sbox_inv(sr_inv[15:8]), aes_sbox_inv(sr_inv[7:0])};
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// AES 64-bit middle round decryption by applying inverse shift-rows, inverse sbox and inverse mix-columns to all bytes
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assign aes64dsm_gen = {aes_mixcolumn_inv(aes64ds_gen[63:32]), aes_mixcolumn_inv(aes64ds_gen[31:0])};
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// AES 64-bit keySchedule decryption by applying inverse mix-columns on rs1
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assign aes64im_gen = {aes_mixcolumn_inv(fu_data_i.operand_a[63:32]), aes_mixcolumn_inv(fu_data_i.operand_a[31:0])};
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// AES Key Schedule results
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// AES Key Schedule part by XORing different slices of rs1 and rs2
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assign aes64ks2_gen = {(fu_data_i.operand_a[63:32] ^ fu_data_i.operand_b[31:0] ^ fu_data_i.operand_b[63:32]), (fu_data_i.operand_a[63:32] ^ fu_data_i.operand_b[31:0])};
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// AES Key Schedule part by substituting round constant based on round number(from instruction), rotations and forward subword substitutions
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assign aes64ks1i_gen = (orig_instr_aes[3:0] <= 4'hA) ? {((aes_subword_fwd((orig_instr_aes[3:0] == 4'hA) ? fu_data_i.operand_a[63:32] : ((fu_data_i.operand_a[63:32] >> 8) | (fu_data_i.operand_a[63:32] << 24)))) ^ (aes_decode_rcon(orig_instr_aes[3:0]))), ((aes_subword_fwd((orig_instr_aes[3:0] == 4'hA) ? fu_data_i.operand_a[63:32] : ((fu_data_i.operand_a[63:32] >> 8) | (fu_data_i.operand_a[63:32] << 24)))) ^ (aes_decode_rcon(orig_instr_aes[3:0])))} : 64'h0;
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end
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end
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@ -727,4 +727,24 @@ module ex_stage
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assign gpaddr_to_be_flushed = '0;
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end
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// // ----------------
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// // Scalar Cryptography Unit
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// // ----------------
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// generate
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// if (CVA6Cfg.ZKN) begin : crypto_gen
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// crypto_fu #(
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// .CVA6Cfg (CVA6Cfg),
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// .fu_data_t(fu_data_t)
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// ) crypto_fu_i (
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// .clk_i,
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// .rst_ni,
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// .fu_data_i (one_cycle_data),
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// .result_o (crypto_result),
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// .orig_instr_aes (orig_instr_aes_i)
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// );
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// end else begin : no_crypto_gen
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// end
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// endgenerate
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endmodule
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@ -903,6 +903,7 @@ package ariane_pkg;
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end
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return result;
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endfunction
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// AES Sbox implementation based on https://github.com/riscv/riscv-crypto
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// AES Sbox Forward
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function automatic logic [7:0] aes_sbox_fwd(input logic [7:0] in_byte);
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logic [20:0] expanded;
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@ -887,10 +887,7 @@ def load_config(args, cwd):
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elif base in ("cv64a6_imafdc_sv39_wb"):
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args.mabi = "lp64d"
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args.isa = "rv64gc_zba_zbb_zbs_zbc"
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elif base in ("cv64a6_imafdc_sv39_hpdcache_wb"):
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args.mabi = "lp64d"
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args.isa = "rv64gc_zba_zbb_zbs_zbc"
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elif base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache"):
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elif base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_hpdcache_wb"):
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args.mabi = "lp64d"
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args.isa = "rv64gc_zba_zbb_zbs_zbc_zbkb_zbkx_zkne_zknd"
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elif base == "cv32a60x":
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