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Move PLIC to 32 bit APB interface

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Florian Zaruba 2018-11-05 15:36:46 +01:00
parent 04270a0499
commit 0ec70e67f1
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4 changed files with 101 additions and 33 deletions
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117
fpga/src/ariane_peripherals.sv
View file

@ -37,36 +37,102 @@ module ariane_peripherals #(
logic [ariane_soc::NumSources-1:0] irq_sources;
REG_BUS #(
.ADDR_WIDTH ( AxiAddrWidth ),
.DATA_WIDTH ( AxiDataWidth )
.ADDR_WIDTH ( 32 ),
.DATA_WIDTH ( 32 )
) reg_bus (clk_i);
AXI_LITE #(
.AXI_ADDR_WIDTH ( AxiAddrWidth ),
.AXI_DATA_WIDTH ( AxiDataWidth )
) axi_lite_plic ();
logic plic_penable;
logic plic_pwrite;
logic [31:0] plic_paddr;
logic plic_psel;
logic [31:0] plic_pwdata;
logic [31:0] plic_prdata;
logic plic_pready;
logic plic_pslverr;
axi_to_axi_lite i_axi_to_axi_lite_eth (
.clk_i,
.rst_ni,
.testmode_i ( 1'b0 ),
.in ( plic ),
.out ( axi_lite_plic )
axi2apb_64_32 #(
.AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
.AXI4_RDATA_WIDTH ( AxiDataWidth ),
.AXI4_WDATA_WIDTH ( AxiDataWidth ),
.AXI4_ID_WIDTH ( $bits(uart.aw_id) ),
.AXI4_USER_WIDTH ( $bits(uart.aw_user) ),
.BUFF_DEPTH_SLAVE ( 2 ),
.APB_ADDR_WIDTH ( 32 )
) i_axi2apb_64_32_plic (
.ACLK ( clk_i ),
.ARESETn ( rst_ni ),
.test_en_i ( 1'b0 ),
.AWID_i ( plic.aw_id ),
.AWADDR_i ( plic.aw_addr ),
.AWLEN_i ( plic.aw_len ),
.AWSIZE_i ( plic.aw_size ),
.AWBURST_i ( plic.aw_burst ),
.AWLOCK_i ( plic.aw_lock ),
.AWCACHE_i ( plic.aw_cache ),
.AWPROT_i ( plic.aw_prot ),
.AWREGION_i( plic.aw_region ),
.AWUSER_i ( plic.aw_user ),
.AWQOS_i ( plic.aw_qos ),
.AWVALID_i ( plic.aw_valid ),
.AWREADY_o ( plic.aw_ready ),
.WDATA_i ( plic.w_data ),
.WSTRB_i ( plic.w_strb ),
.WLAST_i ( plic.w_last ),
.WUSER_i ( plic.w_user ),
.WVALID_i ( plic.w_valid ),
.WREADY_o ( plic.w_ready ),
.BID_o ( plic.b_id ),
.BRESP_o ( plic.b_resp ),
.BVALID_o ( plic.b_valid ),
.BUSER_o ( plic.b_user ),
.BREADY_i ( plic.b_ready ),
.ARID_i ( plic.ar_id ),
.ARADDR_i ( plic.ar_addr ),
.ARLEN_i ( plic.ar_len ),
.ARSIZE_i ( plic.ar_size ),
.ARBURST_i ( plic.ar_burst ),
.ARLOCK_i ( plic.ar_lock ),
.ARCACHE_i ( plic.ar_cache ),
.ARPROT_i ( plic.ar_prot ),
.ARREGION_i( plic.ar_region ),
.ARUSER_i ( plic.ar_user ),
.ARQOS_i ( plic.ar_qos ),
.ARVALID_i ( plic.ar_valid ),
.ARREADY_o ( plic.ar_ready ),
.RID_o ( plic.r_id ),
.RDATA_o ( plic.r_data ),
.RRESP_o ( plic.r_resp ),
.RLAST_o ( plic.r_last ),
.RUSER_o ( plic.r_user ),
.RVALID_o ( plic.r_valid ),
.RREADY_i ( plic.r_ready ),
.PENABLE ( plic_penable ),
.PWRITE ( plic_pwrite ),
.PADDR ( plic_paddr ),
.PSEL ( plic_psel ),
.PWDATA ( plic_pwdata ),
.PRDATA ( plic_prdata ),
.PREADY ( plic_pready ),
.PSLVERR ( plic_pslverr )
);
axi_lite_to_reg #(
.ADDR_WIDTH ( AxiAddrWidth ),
.DATA_WIDTH ( AxiDataWidth )
) i_axi_lite_to_reg (
.clk_i,
.rst_ni,
.axi_i ( axi_lite_plic ), // AXI Lite
.reg_o ( reg_bus )
apb_to_reg i_apb_to_reg (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.penable_i ( plic_penable ),
.pwrite_i ( plic_pwrite ),
.paddr_i ( plic_paddr ),
.psel_i ( plic_psel ),
.pwdata_i ( plic_pwdata ),
.prdata_o ( plic_prdata ),
.pready_o ( plic_pready ),
.pslverr_o ( plic_pslverr ),
.reg_o ( reg_bus )
);
plic #(
.ADDR_WIDTH ( AxiAddrWidth ),
.DATA_WIDTH ( AxiDataWidth ),
.ADDR_WIDTH ( 32 ),
.DATA_WIDTH ( 32 ),
.ID_BITWIDTH ( 3 ), // TODO (zarubaf): Find propper width
.PARAMETER_BITWIDTH ( 3 ), // TODO (zarubaf): Find propper width
.NUM_TARGETS ( ariane_soc::NumTargets ),
@ -75,10 +141,13 @@ module ariane_peripherals #(
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.irq_sources_i ( irq_sources ),
.eip_targets_o ( ),
.eip_targets_o ( ),
.external_bus_io ( reg_bus )
);
// TODO(zarubaf): Remove once PLIC is working
assign irq_o = '0;
// ---------------
// UART
// ---------------
@ -99,7 +168,7 @@ module ariane_peripherals #(
.AXI4_USER_WIDTH ( $bits(uart.aw_user) ),
.BUFF_DEPTH_SLAVE ( 2 ),
.APB_ADDR_WIDTH ( 32 )
) i_axi2apb_64_32 (
) i_axi2apb_64_32_uart (
.ACLK ( clk_i ),
.ARESETn ( rst_ni ),
.test_en_i ( 1'b0 ),

13
src/plic/plic_claim_complete_tracker.sv
View file

@ -89,12 +89,11 @@ module plic_claim_complete_tracker #(
save_claims_array_q[id][counter] <= 1;
end else begin
//if a complete is issued, check if that gateway has previously been claimed by
//this target and forward the
//complete message to that gateway. if no claim has previously been issued, the
//complete message is ignored
//integer complete_id = target_irq_completes_identifier_i[counter];
// if a complete is issued, check if that gateway has previously been claimed by
// this target and forward the
// complete message to that gateway. if no claim has previously been issued, the
// complete message is ignored
// integer complete_id = target_irq_completes_identifier_i[counter];
complete_id = target_irq_completes_identifier_i[counter];
if (target_irq_completes_i[counter] && (save_claims_array_q[complete_id][counter] > 0)) begin
@ -132,4 +131,4 @@ module plic_claim_complete_tracker #(
end
end
endmodule //plic_claim_complete_tracker
endmodule //plic_claim_complete_tracker

2
src/plic/plic_interface.sv
View file

@ -120,7 +120,7 @@ module plic_interface #(
always_comb begin : proc_address_map
// default values
funct = INV;
// only alligned access is allowed:
// only aligned access is allowed:
if (word_offset == '0) begin
// we have now an word alligned access -> check out page offset to determine
// what type of access this is.

2
src/register_interface

@ -1 +1 @@
Subproject commit 46e07bcdad7f9873c7227349c9766c3089eaa8cd
Subproject commit d10dce04b7211da044d31baaa06c7044c84083d9