update riscv-isa-manual to riscv-isa-release-c8c8075-2024-06-12 (#2253)

docs/04_cv32a65x/riscv/Makefile

@@ -15,19 +15,19 @@ setup:
 
 priv-pdf: setup
 	cd build/riscv-isa-manual/build; make priv-pdf
-	cp ./build/riscv-isa-manual/build/priv-isa-asciidoc.pdf priv-isa-cv32a65x.pdf
+	cp ./build/riscv-isa-manual/build/riscv-privileged.pdf priv-isa-cv32a65x.pdf
 
 priv-html: setup
 	cd build/riscv-isa-manual/build; make priv-html
-	cp ./build/riscv-isa-manual/build/priv-isa-asciidoc.html priv-isa-cv32a65x.html
+	cp ./build/riscv-isa-manual/build/riscv-privileged.html priv-isa-cv32a65x.html
 
 unpriv-pdf: setup
 	cd build/riscv-isa-manual/build; make unpriv-pdf
-	cp ./build/riscv-isa-manual/build/unpriv-isa-asciidoc.pdf unpriv-isa-cv32a65x.pdf
+	cp ./build/riscv-isa-manual/build/riscv-unprivileged.pdf unpriv-isa-cv32a65x.pdf
 
 unpriv-html: setup
 	cd build/riscv-isa-manual/build; make unpriv-html
-	cp ./build/riscv-isa-manual/build/unpriv-isa-asciidoc.html unpriv-isa-cv32a65x.html
+	cp ./build/riscv-isa-manual/build/riscv-unprivileged.html unpriv-isa-cv32a65x.html
 
 clean:
 	rm -rf build

docs/04_cv32a65x/riscv/riscv-isa-manual

@@ -1 +1 @@
-Subproject commit 1bec7d34914aa1a2a890b4fca30af519ba539e7b
+Subproject commit c8c8075a6a71be67ac723528070e3e50ff7586b2

docs/04_cv32a65x/riscv/src/bfloat16.adoc

@@ -0,0 +1,6 @@
+[[bf16]]
+== "BF16" Extensions for for BFloat16-precision Floating-Point, Version 1.0
+
+ifeval::[{RVZfbf-RZvfbf} == false]
+{ohg-config}: These extensions are not supported.
+endif::[]

docs/04_cv32a65x/riscv/src/colophon.adoc

@@ -7,7 +7,7 @@
 This document describes the RISC-V unprivileged architecture tailored for
 OpenHW Group {ohg-config}.
 
-[.big]*_Preface to Document Version 20240528_*
+[.big]*_Preface to Document Version 20240612_*
 
 This document describes the RISC-V unprivileged architecture.
 

docs/04_cv32a65x/riscv/src/config.adoc

@@ -11,9 +11,11 @@
 :RVS: false
 :RVU: false
 :RVV: false
+:RVZabha: false
 :RVZacas: false
 :RVZawrs: false
 :RVZfa: false
+:RVZfbf-RZvfbf: false
 :RVZfh: false
 :RVZfinx: false
 :RVZicbo: false
@@ -29,11 +31,13 @@
 :RVZsmcdeleg: false
 :RVZsmcntrpmf: false
 :RVZsmcsrind-RVZsscsrind: false
+:RVZsmdbltrp: false
 :RVZsmepmp: false
 :RVZsmmpm: false
 :RVZsmrnmi: false
 :RVZsmstateen: false
 :RVZsscofpmf: false
+:RVZssdbltrp: false
 :RVZsstc: false
 :RVZtso: false
 :RVZvk: false

docs/04_cv32a65x/riscv/src/machine.adoc

@@ -529,7 +529,8 @@ ifeval::[{ohg-config} != CV32A65X]
   {bits:  1, name: 'MPV'},
   {bits:  1, name: 'WPRI'},
   {bits:  1, name: 'MPELP'},
-  {bits: 21, name: 'WPRI'},
+  {bits:  1, name: 'MDT'},
+  {bits: 20, name: 'WPRI'},
   {bits:  1, name: 'SD'},
 ], config:{lanes: 4, hspace:1024}}
 ....
@@ -553,8 +554,13 @@ endif::[]
   {bits:  4, name: 'WPRI'},
   {bits:  1, name: 'SBE'},
   {bits:  1, name: 'MBE'},
-  {bits: 26, name: 'WPRI'},
-], config:{lanes: 1, hspace:1024}}
+  {bits:  1, name: 'GVA'},
+  {bits:  1, name: 'MPV'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'MPELP'},
+  {bits:  1, name: 'MDT'},
+  {bits: 21, name: 'WPRI'},
+], config:{lanes: 2, hspace:1024}}
 ....
 
 [[privstack]]
@@ -692,6 +698,78 @@ ifeval::[{RVS} == false]
 and UPP are read-only 0.
 endif::[]
 
+[[machine-double-trap]]
+===== Double Trap Control in `mstatus` Register
+
+ifeval::[{RVZsmdbltrp} == true]
+A double trap typically arises during a sensitive phase in trap handling
+operations -- when an exception or interrupt occurs while the trap handler (the
+component responsible for managing these events) is in a non-reentrant state.
+This non-reentrancy usually occurs in the early phase of trap handling, wherein
+the trap handler has not yet preserved the necessary state to handle and resume
+from the trap. The occurrence of a trap during this phase can lead to an
+overwrite of critical state information, resulting in the loss of data needed to
+recover from the initial trap. The trap that caused this critical error
+condition is henceforth called the _unexpected trap_. Trap handlers are designed
+to neither enable interrupts nor cause exceptions during this phase of handling.
+However, managing Hardware-Error exceptions,  which may occur unpredictably,
+presents significant challenges in trap handler implementation due to the
+potential risk of a double trap.
+
+The M-mode-disable-trap (`MDT`) bit is a WARL field introduced by the Smdbltrp
+extension. Upon reset, the `MDT` field is set to 1. When the `MDT` bit is set to
+1 by an explicit CSR write, the `MIE` (Machine Interrupt Enable) bit is cleared
+to 0. For RV64, this clearing occurs regardless of the value written, if any, to
+the `MIE` bit by the same write. The `MIE` bit can only be set to 1 by an
+explicit CSR write if the `MDT` bit is already 0 or, for RV64, is being set to 0
+by the same write (For RV32, the `MDT` bit is in `mstatush` and the `MIE` bit in
+`mstatus` register).
+
+When a trap is to be taken into M-mode, if the `MDT` bit is currently 0, it is
+then set to 1, and the trap is delivered as expected. However, if `MDT` is
+already set to 1, then this is an _unexpected trap_. Additionally, when the
+Smrnmi extension is implemented, a trap that occurs when executing in M-mode
+with the `mnstatus.NMIE` set to 0 is an _unexpected trap_.
+
+In the event of a _unexpected trap_, the handling is as follows:
+
+* When the Smrnmi extension is implemented and `mnstatus.NMIE` is 1, the hart
+  traps to the RNMI handler. To deliver this trap, the `mnepc` and `mncause`
+  registers are written with the values that the _unexpected trap_ would have
+  written to the `mepc` and `mcause` registers respectively. The privilege
+  mode information fields in the `mnstatus` register are written to indicate
+  M-mode and its `NMIE` field is set to 0.
+
+[NOTE]
+====
+The consequence of this specification is that on occurrence of double trap the
+RNMI handler is not provided with information that a trap would report in the
+`mtval` and the `mtval2` registers. This information, if needed, may be obtained
+by the RNMI handler by decoding the instruction at the address in `mnepc` and
+examining its source register contents.
+====
+
+* When the Smrnmi extension is not implemented, or if the Smrnmi extension is
+  implemented and `mnstatus.NMIE` is 0, the hart enters a critical-error state
+  without updating any architectural state including the `pc`. This state
+  involves ceasing execution, disabling all interrupts (including NMIs), and
+  asserting a `critical-error` signal to the platform.
+
+[NOTE]
+====
+The actions performed by the platform on assertion of a `critical-error` signal
+by a hart are platform specific. The range of possible actions include restarting
+the affected hart or restarting the entire platform among others.
+====
+
+An `MRET` instruction sets the `MDT` bit to 0.
+endif::[]
+
+ifeval::[{RVZsmdbltrp} == true]
+[{ohg-config}] As Double Trap Control (Smdbltrp extension) is not implemented,
+MDT field is read-only 0.
+endif::[]
+
 [[xlen-control]]
 ===== Base ISA Control in `mstatus` Register
 
@@ -1230,6 +1308,8 @@ unconfigure or disable/enable instructions.
 
 <<<
 
+[[fsxsstates]]
+.FS, VS, and XS state transitions.
 [width=75,align=center,float=center,cols="<,<,<,<,<"]
 |===
 |Current State +
@@ -1333,9 +1413,7 @@ Off
 Off
 |===
 
-[[fsxsstates]]
 [width=75,align=center,float=center,cols="<,<,<,<,<"]
-.FS, FS, and XS state transitions.
 |===
 5+^|Execute instruction to enable unit
 
@@ -1586,6 +1664,8 @@ interrupt delegation control is located in bit 5).
 For exceptions that cannot occur in less privileged modes, the
 corresponding `medeleg` bits should be read-only zero. In particular,
 `medeleg`[11] is read-only zero.
+
+The `medeleg`[16] is read-only zero as double trap is not delegatable.
 endif::[]
 
 ifeval::[{RVU} == false]
@@ -1876,13 +1956,6 @@ include::images/bytefield/hpmevents.adoc[]
 The `mhpmcounters` are *WARL* registers that support up to 64 bits of
 precision on RV32 and RV64.
 
-[NOTE]
-====
-A future revision of this specification will define a mechanism to
-generate an interrupt when a hardware performance monitor counter
-overflows.
-====
-
 When XLEN=32, reads of the `mcycle`, `minstret`, `mhpmcounter__n__`, and `mhpmevent__n__`
 CSRs return bits 31-0 of the corresponding register, and writes change
 only bits 31-0; reads of the `mcycleh`, `minstreth`, `mhpmcounter__n__h`, and `mhpmevent__n__h`
@@ -2223,6 +2296,7 @@ _Designated for platform use_
 0 +
 0 +
 0 +
+0 +
 0
 |0 +
 1 +
@@ -2240,7 +2314,8 @@ _Designated for platform use_
 13 +
 14 +
 15 +
-16-17 +
+16 +
+17 +
 18 +
 19 +
 20-23 +
@@ -2264,6 +2339,7 @@ Instruction page fault +
 Load page fault +
 _Reserved_ +
 Store/AMO page fault +
+Double trap +
 _Reserved_ +
 Software check +
 Hardware error +
@@ -2550,7 +2626,8 @@ privileged than M.
   {bits:  1, name: 'CBZE'},
   {bits: 24, name: 'WPRI'},
   {bits:  2, name: 'PMM'},
-  {bits: 26, name: 'WPRI'},
+  {bits: 25, name: 'WPRI'},
+  {bits:  1, name: 'DTE'},
   {bits:  1, name: 'CDE'},
   {bits:  1, name: 'ADUE'},
   {bits:  1, name: 'PBMTE'},
@@ -2661,6 +2738,11 @@ the following rules apply to privilege modes that are less than M:
 * The `henvcfg.SSE` and `senvcfg.SSE` fields will read as zero and are read-only.
 * `SSAMOSWAP.W/D` raises an illegal-instruction exception.
 
+The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `menvcfg`.
+When `menvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not
+implemented. When Ssdbltrp is not implemented `sstatus.SDT`, `vsstatus.SDT`, and
+`henvcfg.DTE` bits are read-only zero.
+
 When XLEN=32, `menvcfgh` is a 32-bit read/write register
 that aliases bits 63:32 of `menvcfg`.
 The `menvcfgh` register does not exist when XLEN=64.
@@ -3035,12 +3117,6 @@ privilege mode, either immediately on encountering the WFI or after some
 interval to initiate a machine-mode transition to a lower power state,
 for example.
 
-As implementations are free to implement WFI as a NOP, software must
-explicitly check for any relevant pending but disabled interrupts in the
-code following an WFI, and should loop back to the WFI if no suitable
-interrupt was detected. The `mip` register can be interrogated
-to determine the presence of any interrupt in machine.
-
 ***
 
 The same "wait-for-event" template might be used for possible future
@@ -3796,9 +3872,6 @@ are *WARL*.
 include::images/bytefield/pmpaddr-rv32.adoc[]
 endif::[]
 
-
-
-
 <<pmpcfg>> shows the layout of a PMP configuration
 register. The R, W, and X bits, when set, indicate that the PMP entry
 permits read, write, and instruction execution, respectively. When one
@@ -3998,7 +4071,6 @@ If a PMP entry matches all bytes of an access, then the L, R, W, and X
 bits determine whether the access succeeds or fails. If the L bit is
 clear and the privilege mode of the access is M, the access succeeds.
 
-
 ifeval::[{RVU} == true]
 Otherwise, if the L bit is set or the privilege mode of the access is S
 or U, then the access succeeds only if the R, W, or X bit corresponding

docs/04_cv32a65x/riscv/src/priv-preface.adoc

@@ -6,10 +6,10 @@
 This document describes the RISC-V privileged architecture tailored for
 OpenHW Group {ohg-config}.
 
-[.big]*_Preface to Version 20240528_*
+[.big]*_Preface to Version 20240612_*
 
 This document describes the RISC-V privileged architecture. This
-release, version 20240528, contains the following versions of the RISC-V ISA
+release, version 20240612, contains the following versions of the RISC-V ISA
 modules:
 
 [%autowidth,float="center",align="center",cols="^,<,^",options="header",]
@@ -22,6 +22,7 @@ modules:
 **Smcntrpmf* +
 *Smrnmi Extension* +
 *Smcdeleg* +
+*Smdbltrp* +
 _Supervisor ISA_ +
 *Svade Extension* +
 *Svnapot Extension* +
@@ -30,7 +31,9 @@ _Supervisor ISA_ +
 *Svadu Extension* +
 *Sstc* +
 *Sscofpmf* +
-*Hypervisor ISA*
+*Ssdbltrp* +
+*Hypervisor ISA* +
+_Shlcofideleg_
 
 |_1.13_ +
 *1.0* +
@@ -39,6 +42,7 @@ _Supervisor ISA_ +
 *1.0* +
 *1.0* +
 *1.0* +
+*1.0* +
 _1.13_ +
 *1.0* +
 *1.0* +
@@ -47,7 +51,9 @@ _1.13_ +
 *1.0* +
 *1.0* +
 *1.0* +
-*1.0*
+*1.0* +
+*1.0* +
+_0.1_
 
 |_Draft_ +
 *Ratified* +
@@ -57,6 +63,7 @@ _1.13_ +
 *Ratified* +
 *Ratified* +
 _Draft_ +
+_Draft_ +
 *Ratified* +
 *Ratified* +
 *Ratified* +
@@ -64,7 +71,9 @@ _Draft_ +
 *Ratified* +
 *Ratified* +
 *Ratified* +
-*Ratified*
+_Draft_ +
+*Ratified* +
+_Draft_
 |===
 
 The following changes have been made since version 1.12 of the Machine and
@@ -77,6 +86,8 @@ anticipated to cause software portability problems in practice:
 Additionally, the following compatible changes have been
 made to the Machine and Supervisor ISAs since version 1.12:
 
+* Defined the `misa`.B field to reflect that the B extension has been
+implemented.
 * Defined the `misa`.V field to reflect that the V extension has been
 implemented.
 * Defined the RV32-only `medelegh` and `hedelegh` CSRs.
@@ -86,7 +97,7 @@ implemented.
 * Defined hardware error and software check exception codes.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
-* Exposed count-overflow interrups to VS-mode.
+* Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension.
 
 Finally, the following clarifications and document improvments have been made
 since the last document release:

docs/04_cv32a65x/riscv/src/riscv-privileged.adoc

@@ -2,7 +2,7 @@
 = The RISC-V Instruction Set Manual for CV32A65X: Volume II: Privileged Architecture
 :description: Volume II - Privileged Architecture
 :company: RISC-V.org
-:revnumber: 20240528
+:revnumber: 20240612
 //:revremark: Pre-release version
 //development: assume everything can change
 //stable: assume everything could change
@@ -100,11 +100,13 @@ include::smepmp.adoc[]
 include::smcntrpmf.adoc[]
 include::rnmi.adoc[]
 include::smcdeleg.adoc[]
+include::smdbltrp.adoc[]
 include::supervisor.adoc[]
 include::sstc.adoc[]
 include::sscofpmf.adoc[]
 include::hypervisor.adoc[]
 include::priv-cfi.adoc[]
+include::ssdbltrp.adoc[]
 include::priv-insns.adoc[]
 include::priv-history.adoc[]
 include::bibliography.adoc[]

docs/04_cv32a65x/riscv/src/riscv-unprivileged.adoc

@@ -2,7 +2,7 @@
 = The RISC-V Instruction Set Manual for CV32A65X: Volume I - Unprivileged Architecture
 :description: Volume I - Unprivileged Architecture
 :company: RISC-V.org
-:revnumber: 20240528
+:revnumber: 20240612
 //:revremark: Pre-release version
 :url-riscv: http://riscv.org
 :doctype: book
@@ -29,7 +29,8 @@
 :bibtex-throw: false
 :icons: font
 :lang: en
-:listing-caption: Example
+:example-caption: Example
+:listing-caption: Listing
 :sectnums:
 :toc: left
 :toclevels: 5
@@ -43,6 +44,8 @@ endif::[]
 :chapter-refsig: Chapter
 :section-refsig: Section
 :appendix-refsig: Appendix
+// Uncomment :data-uri: if your eBook reader is not capable of rendering
+// embedded images. One known affected device is PocketBook InkPad 3.
 :data-uri:
 :hide-uri-scheme:
 :stem: latexmath
@@ -181,6 +184,7 @@ include::m-st-ext.adoc[]
 include::a-st-ext.adoc[]
 include::zawrs.adoc[]
 include::zacas.adoc[]
+include::zabha.adoc[]
 include::rvwmo.adoc[]
 include::ztso-st-ext.adoc[]
 include::cmo.adoc[]
@@ -188,6 +192,7 @@ include::f-st-ext.adoc[]
 include::d-st-ext.adoc[]
 include::q-st-ext.adoc[]
 include::zfh.adoc[]
+include::bfloat16.adoc[]
 include::zfa.adoc[]
 include::zfinx.adoc[]
 include::c-st-ext.adoc[]
@@ -198,6 +203,7 @@ include::p-st-ext.adoc[]
 include::v-st-ext.adoc[]
 include::scalar-crypto.adoc[]
 include::vector-crypto.adoc[]
+include::unpriv-cfi.adoc[]
 include::rv-32-64g.adoc[]
 include::extending.adoc[]
 include::naming.adoc[]

docs/04_cv32a65x/riscv/src/rv-32-64g.adoc

@@ -194,6 +194,7 @@ endif::[]
 
 <<<
 ifeval::[{RVA} == true]
+
 [%autowidth.stretch,float="center",align="center",cols="^2m,^2m,^2m,^2m,<2m,>3m, <4m, >4m, <4m, >4m, <4m, >4m, <4m, >4m, <6m"]
 |===
 15+^|

docs/04_cv32a65x/riscv/src/smdbltrp.adoc

@@ -0,0 +1,6 @@
+[[smdbltrp]]
+== "Smdbltrp" Double Trap Extension, Version 1.0
+
+ifeval::[{RVZsmdbltrp} == false]
+{ohg-config}: This extension is not supported.
+endif::[]

docs/04_cv32a65x/riscv/src/ssdbltrp.adoc

@@ -0,0 +1,6 @@
+[[ssdbltrp]]
+== "Ssdbltrp" Double Trap Extension, Version 1.0
+
+ifeval::[{RVZssdbltrp} == false]
+{ohg-config}: This extension is not supported.
+endif::[]

docs/04_cv32a65x/riscv/src/unpriv-cfi.adoc

@@ -0,0 +1,10 @@
+[[unpriv-cfi]]
+== Control-flow Integrity (CFI)
+
+ifeval::[{RVZicfiss} == false]
+{ohg-config}: The Zicfiss extension is not supported.
+endif::[]
+
+ifeval::[{RVZicfilp} == false]
+{ohg-config}: The Zicfilp extension is not supported.
+endif::[]

docs/04_cv32a65x/riscv/src/vector-crypto.adoc

@@ -1,5 +1,5 @@
 [[vector-crypto]]
-== Cryptography Extensions: Vector Instructions, Version 1.0.0
+== Cryptography Extensions: Vector Instructions, Version 1.0
 
 ifeval::[{RVZvk} == false]
 {ohg-config}: These extensions are not supported.

docs/04_cv32a65x/riscv/src/zabha.adoc

@@ -0,0 +1,6 @@
+[[zabha]]
+== "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0.0
+
+ifeval::[{RVZabha} == false]
+{ohg-config}: This extension is not supported.
+endif::[]