Add stub modules for nddcache [ci skip]

include/ariane_pkg.sv

@@ -1,5 +1,5 @@
 
-/* File:   ariane_pkg.svh
+/* File:   ariane_pkg.sv
  * Author: Florian Zaruba <zarubaf@ethz.ch>
  * Date:   8.4.2017
  *

include/nbdcache_pkg.sv

@@ -1,4 +1,4 @@
-/* File:   ariane_pkg.svh
+/* File:   nbdcache_pkh.sv
  * Author: Florian Zaruba <zarubaf@ethz.ch>
  * Date:   13.10.2017
  *
@@ -12,5 +12,12 @@
 package nbdcache_pkg;
 
     typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } req_t;
+    typedef enum logic { LOAD_MISS, STORE_MISS } miss_t;
+
+    typedef struct packed {
+        logic        valid;
+        miss_t       type;
+        logic [55:0] addr;
+    } mshr_t;
 
 endpackage

src/cache_ctrl.sv

@@ -0,0 +1,16 @@
+/* File:   cache_ctrl.svh
+ * Author: Florian Zaruba <zarubaf@ethz.ch>
+ * Date:   14.10.2017
+ *
+ * Copyright (C) 2017 ETH Zurich, University of Bologna
+ * All rights reserved.
+ *
+ * Description: Cache controller
+ */
+module cache_ctrl (
+    input  logic clk_i,    // Clock
+    input  logic rst_ni  // Asynchronous reset active low
+
+);
+
+endmodule

src/lsu.sv

@@ -132,6 +132,7 @@ module lsu #(
     logic [2:0][63:0]         data_rdata_o;
     amo_t [2:0]               amo_op_i;
 
+    // AMO operations always go through the load unit
     assign amo_op_i[0] = AMO_NONE;
     assign amo_op_i[2] = AMO_NONE;
 
@@ -139,7 +140,7 @@ module lsu #(
     // Port 0: PTW
     // Port 1: Load Unit
     // Port 2: Store Unit
-    nb_dcache i_nb_dcache (
+    nbdcache i_nbdcache (
         // to D$
         .data_if           ( data_if                 ),
         // from PTW, Load Unit and Store Unit

src/nbdcache.sv

@@ -35,6 +35,7 @@ module nb_dcache #(
     input  logic                           amo_commit_i, // commit atomic memory operation
     output logic                           amo_valid_o,  // we have a valid AMO result
     output logic [63:0]                    amo_result_o, // result of atomic memory operation
+    input  logic                           amo_flush_i,  // forget about AMO
     // Request ports
     input  logic [2:0][INDEX_WIDTH-1:0]    address_index_i,
     input  logic [2:0][TAG_WIDTH-1:0]      address_tag_i,