mirror of
https://github.com/openhwgroup/cva6.git
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Makefile: Implement plateforms defined in cva6 specification (#769)
* Makefile: Implement the plateforms defined in cva6 specification
target variable can take cv64a6_imacfd_sv39, cv32a6_imac_sv0,
cv32a6_imac_sv32, cv32a6_imacf_sv32
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
* Fix plateform name: from imacfd to imafdc
from imacf to imafc
Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
This commit is contained in:
JeanRochCoulon
GitHub
parent
f5c68710fa
commit
1094082d75
8 changed files with 338 additions and 8 deletions
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@ -202,7 +202,7 @@ sources:
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- corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv
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- target: not(cv32a6)
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files:
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- core/include/cv64a6_imacfd_sv39_config_pkg.sv
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- core/include/cv64a6_imafdc_sv39_config_pkg.sv
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- target: cv32a6
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files:
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- core/include/cv32a6_imac_sv0_config_pkg.sv
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12
Makefile
12
Makefile
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@ -71,13 +71,13 @@ ifdef spike-tandem
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endif
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endif
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# target takes one of the following cva6 hardware configuration:
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# cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32
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target ?= cv64a6_imafdc_sv39
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# Sources
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# Package files -> compile first
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ifeq ($(findstring 32, $(variant)),32)
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ariane_pkg := core/include/cv32a6_imac_sv0_config_pkg.sv
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else
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ariane_pkg := core/include/cv64a6_imacfd_sv39_config_pkg.sv
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endif
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ariane_pkg := core/include/$(target)_config_pkg.sv
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ariane_pkg += core/include/riscv_pkg.sv \
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corev_apu/riscv-dbg/src/dm_pkg.sv \
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core/include/ariane_pkg.sv \
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@ -227,7 +227,7 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
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corev_apu/tb/common/SimJTAG.sv
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# SV32 MMU for CV32, SV39 MMU for CV64
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ifeq ($(findstring 32, $(variant)),32)
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ifeq ($(findstring 32, $(target)),32)
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src += $(wildcard core/mmu_sv32/*.sv)
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else
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src += $(wildcard core/mmu_sv39/*.sv)
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150
core/Flist.cv32a6_imac_sv32
Normal file
150
core/Flist.cv32a6_imac_sv32
Normal file
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@ -0,0 +1,150 @@
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//////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2021 OpenHW Group
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Manifest for the CVA6 CORE RTL model.
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// - This is a CORE-ONLY manifest.
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// - Relevent synthesis and simulation scripts/Makefiles must set the shell
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// ENV variable CVA6_REPO_DIR.
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//
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///////////////////////////////////////////////////////////////////////////////
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+define+WT_DCACHE
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+incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/include/
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+incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
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+incdir+${CVA6_REPO_DIR}/common/local/util/
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${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
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// Broken (?) dependencies in packages:
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// - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
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// (ariane should not depend on debug-module)
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${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
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// TODO: should not be needed.
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${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
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${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
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// TODO: ariane_axi_pkg is dependent on this.
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${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
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${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
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${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
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// Packages
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${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
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${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
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${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
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${CVA6_REPO_DIR}/core/include/axi_intf.sv
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${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
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// Common Cells
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/fifo_v3.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/lfsr.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/lzc.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/rr_arb_tree.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/shift_reg.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/unread.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/popcount.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/exp_backoff.sv
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// Floating point unit
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_pkg.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_cast_multi.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_classifier.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_divsqrt_multi.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma_multi.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_noncomp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_block.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_fmt_slice.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_multifmt_slice.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_rounding.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_top.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
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// Top-level source files (not necessarily instantiated at the top of the cva6).
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${CVA6_REPO_DIR}/core/ariane.sv
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${CVA6_REPO_DIR}/core/alu.sv
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// Note: depends on fpnew_pkg, above
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${CVA6_REPO_DIR}/core/fpu_wrap.sv
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${CVA6_REPO_DIR}/core/branch_unit.sv
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${CVA6_REPO_DIR}/core/compressed_decoder.sv
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${CVA6_REPO_DIR}/core/controller.sv
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${CVA6_REPO_DIR}/core/csr_buffer.sv
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${CVA6_REPO_DIR}/core/csr_regfile.sv
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${CVA6_REPO_DIR}/core/decoder.sv
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${CVA6_REPO_DIR}/core/ex_stage.sv
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${CVA6_REPO_DIR}/core/instr_realign.sv
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${CVA6_REPO_DIR}/core/id_stage.sv
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${CVA6_REPO_DIR}/core/issue_read_operands.sv
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${CVA6_REPO_DIR}/core/issue_stage.sv
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${CVA6_REPO_DIR}/core/load_unit.sv
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${CVA6_REPO_DIR}/core/load_store_unit.sv
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${CVA6_REPO_DIR}/core/mult.sv
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${CVA6_REPO_DIR}/core/multiplier.sv
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${CVA6_REPO_DIR}/core/serdiv.sv
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${CVA6_REPO_DIR}/core/perf_counters.sv
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${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
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${CVA6_REPO_DIR}/core/re_name.sv
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// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
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${CVA6_REPO_DIR}/core/scoreboard.sv
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${CVA6_REPO_DIR}/core/store_buffer.sv
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${CVA6_REPO_DIR}/core/amo_buffer.sv
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${CVA6_REPO_DIR}/core/store_unit.sv
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${CVA6_REPO_DIR}/core/commit_stage.sv
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${CVA6_REPO_DIR}/core/axi_shim.sv
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// What is "frontend"?
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${CVA6_REPO_DIR}/core/frontend/btb.sv
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${CVA6_REPO_DIR}/core/frontend/bht.sv
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${CVA6_REPO_DIR}/core/frontend/ras.sv
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${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
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${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
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${CVA6_REPO_DIR}/core/frontend/frontend.sv
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// Cache subsystem
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
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${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
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// Physical Memory Protection
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// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
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${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
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${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
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// Tracer (behavioral code, not RTL)
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${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
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${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
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${CVA6_REPO_DIR}/common/local/util/sram.sv
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// MMU Sv32
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${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
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${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
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${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
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// end of manifest
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150
core/Flist.cv32a6_imafc_sv32
Normal file
150
core/Flist.cv32a6_imafc_sv32
Normal file
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@ -0,0 +1,150 @@
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//////////////////////////////////////////////////////////////////////////////
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//
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// Copyright 2021 OpenHW Group
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//
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// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Manifest for the CVA6 CORE RTL model.
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// - This is a CORE-ONLY manifest.
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// - Relevent synthesis and simulation scripts/Makefiles must set the shell
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// ENV variable CVA6_REPO_DIR.
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//
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///////////////////////////////////////////////////////////////////////////////
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+define+WT_DCACHE
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+incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/include/
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+incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
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+incdir+${CVA6_REPO_DIR}/common/local/util/
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${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
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// Broken (?) dependencies in packages:
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// - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
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// (ariane should not depend on debug-module)
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${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
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// TODO: should not be needed.
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${CVA6_REPO_DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv
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${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
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// TODO: ariane_axi_pkg is dependent on this.
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${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
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${CVA6_REPO_DIR}/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
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${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
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// Packages
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${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
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${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
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${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
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${CVA6_REPO_DIR}/core/include/axi_intf.sv
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${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
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// Common Cells
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/fifo_v3.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/lfsr.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/lzc.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/rr_arb_tree.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/shift_reg.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/unread.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/popcount.sv
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${CVA6_REPO_DIR}/common/submodules/common_cells/src/exp_backoff.sv
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// Floating point unit
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_pkg.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_cast_multi.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_classifier.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_divsqrt_multi.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma_multi.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_fma.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_noncomp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_block.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_fmt_slice.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_opgroup_multifmt_slice.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_rounding.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpnew_top.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
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${CVA6_REPO_DIR}/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
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// Top-level source files (not necessarily instantiated at the top of the cva6).
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${CVA6_REPO_DIR}/core/ariane.sv
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${CVA6_REPO_DIR}/core/alu.sv
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// Note: depends on fpnew_pkg, above
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${CVA6_REPO_DIR}/core/fpu_wrap.sv
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${CVA6_REPO_DIR}/core/branch_unit.sv
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${CVA6_REPO_DIR}/core/compressed_decoder.sv
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${CVA6_REPO_DIR}/core/controller.sv
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${CVA6_REPO_DIR}/core/csr_buffer.sv
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${CVA6_REPO_DIR}/core/csr_regfile.sv
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${CVA6_REPO_DIR}/core/decoder.sv
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${CVA6_REPO_DIR}/core/ex_stage.sv
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${CVA6_REPO_DIR}/core/instr_realign.sv
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${CVA6_REPO_DIR}/core/id_stage.sv
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${CVA6_REPO_DIR}/core/issue_read_operands.sv
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${CVA6_REPO_DIR}/core/issue_stage.sv
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${CVA6_REPO_DIR}/core/load_unit.sv
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${CVA6_REPO_DIR}/core/load_store_unit.sv
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${CVA6_REPO_DIR}/core/mult.sv
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${CVA6_REPO_DIR}/core/multiplier.sv
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${CVA6_REPO_DIR}/core/serdiv.sv
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${CVA6_REPO_DIR}/core/perf_counters.sv
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${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
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${CVA6_REPO_DIR}/core/re_name.sv
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// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
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${CVA6_REPO_DIR}/core/scoreboard.sv
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${CVA6_REPO_DIR}/core/store_buffer.sv
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${CVA6_REPO_DIR}/core/amo_buffer.sv
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${CVA6_REPO_DIR}/core/store_unit.sv
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||||
${CVA6_REPO_DIR}/core/commit_stage.sv
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||||
${CVA6_REPO_DIR}/core/axi_shim.sv
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||||
// What is "frontend"?
|
||||
${CVA6_REPO_DIR}/core/frontend/btb.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/bht.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/ras.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
|
||||
${CVA6_REPO_DIR}/core/frontend/frontend.sv
|
||||
|
||||
// Cache subsystem
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
|
||||
${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
|
||||
|
||||
// Physical Memory Protection
|
||||
// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
|
||||
${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
|
||||
${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
|
||||
|
||||
// Tracer (behavioral code, not RTL)
|
||||
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
|
||||
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
|
||||
${CVA6_REPO_DIR}/common/local/util/sram.sv
|
||||
|
||||
// MMU Sv32
|
||||
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
|
||||
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
|
||||
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
|
||||
|
||||
// end of manifest
|
||||
|
|
@ -31,7 +31,7 @@
|
|||
+incdir+${CVA6_REPO_DIR}/common/submodules/common_cells/src/
|
||||
+incdir+${CVA6_REPO_DIR}/common/local/util/
|
||||
|
||||
${CVA6_REPO_DIR}/core/include/cv64a6_imacfd_sv39_config_pkg.sv
|
||||
${CVA6_REPO_DIR}/core/include/cv64a6_imafdc_sv39_config_pkg.sv
|
||||
// Broken (?) dependencies in packages:
|
||||
// - include/ariane_pkg.sv is dependent on src/riscv-dbg/src/dm_pkg.sv
|
||||
// (ariane should not depend on debug-module)
|
||||
|
|
|
|||
15
core/include/cv32a6_imac_sv32_config_pkg.sv
Normal file
15
core/include/cv32a6_imac_sv32_config_pkg.sv
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
// Copyright 2021 Thales DIS design services SAS
|
||||
//
|
||||
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
|
||||
// You may obtain a copy of the License at https://solderpad.org/licenses/
|
||||
//
|
||||
// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
|
||||
|
||||
|
||||
package cva6_config_pkg;
|
||||
|
||||
localparam CVA6ConfigXlen = 32;
|
||||
|
||||
endpackage
|
||||
15
core/include/cv32a6_imafc_sv32_config_pkg.sv
Normal file
15
core/include/cv32a6_imafc_sv32_config_pkg.sv
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
// Copyright 2021 Thales DIS design services SAS
|
||||
//
|
||||
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
|
||||
// You may obtain a copy of the License at https://solderpad.org/licenses/
|
||||
//
|
||||
// Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
|
||||
|
||||
|
||||
package cva6_config_pkg;
|
||||
|
||||
localparam CVA6ConfigXlen = 32;
|
||||
|
||||
endpackage
|
||||
Loading…
Add table
Add a link
Reference in a new issue