mirror of
https://github.com/openhwgroup/cva6.git
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Make appropriate AXI size requests
This commit is contained in:
Florian Zaruba
parent
cb04234629
commit
11b03190f2
11 changed files with 89 additions and 31 deletions
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@ -104,6 +104,20 @@ package ariane_pkg;
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DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW
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} fu_op;
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// ----------------------
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// Extract Bytes from Op
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// ----------------------
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// TODO: Add atomics
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function automatic logic [1:0] extract_transfer_size (fu_op op);
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case (op)
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LD, SD: return 2'b11;
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LW, LWU, SW: return 2'b10;
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LH, LHU, SH: return 2'b01;
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LB, SB, LBU: return 2'b00;
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default: return 2'b11;
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endcase
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endfunction
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typedef struct packed {
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logic valid;
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logic [63:0] vaddr;
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@ -393,7 +407,7 @@ package ariane_pkg;
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// ----------------------
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// Arithmetic Functions
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// ----------------------s
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// ----------------------
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function automatic logic [63:0] sext32 (logic [31:0] operand);
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return {{32{operand[31]}}, operand[31:0]};
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endfunction
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@ -38,11 +38,12 @@ package nbdcache_pkg;
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typedef struct packed {
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logic valid;
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logic bypass;
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logic [63:0] addr;
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logic [7:0] be;
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logic [1:0] size;
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logic we;
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logic [63:0] wdata;
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logic bypass;
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} miss_req_t;
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typedef struct packed {
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@ -28,6 +28,7 @@ module cache_ctrl #(
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input logic data_req_i,
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input logic data_we_i,
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input logic [7:0] data_be_i,
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input logic [1:0] data_size_i,
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input logic kill_req_i,
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input logic tag_valid_i,
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output logic data_gnt_o,
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@ -67,6 +68,7 @@ module cache_ctrl #(
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logic [INDEX_WIDTH-1:0] index;
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logic [TAG_WIDTH-1:0] tag;
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logic [7:0] be;
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logic [1:0] size;
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logic we;
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logic [63:0] wdata;
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logic bypass;
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@ -118,6 +120,7 @@ module cache_ctrl #(
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mem_req_d.index = address_index_i;
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mem_req_d.tag = address_tag_i;
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mem_req_d.be = data_be_i;
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mem_req_d.size = data_size_i;
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mem_req_d.we = data_we_i;
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mem_req_d.wdata = data_wdata_i;
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// TODO: Check for non-cache able accesses
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@ -164,6 +167,7 @@ module cache_ctrl #(
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state_d = WAIT_TAG; // switch back to WAIT_TAG
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mem_req_d.index = address_index_i;
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mem_req_d.be = data_be_i;
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mem_req_d.size = data_size_i;
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mem_req_d.we = data_we_i;
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mem_req_d.wdata = data_wdata_i;
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mem_req_d.tag = address_tag_i;
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@ -290,13 +294,16 @@ module cache_ctrl #(
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miss_req_o.bypass = mem_req_q.bypass;
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miss_req_o.addr = {mem_req_q.tag, mem_req_q.index};
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miss_req_o.be = mem_req_q.be;
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miss_req_o.size = mem_req_q.size;
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miss_req_o.we = mem_req_q.we;
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miss_req_o.wdata = mem_req_q.wdata;
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// got a grant so go to valid
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if (bypass_gnt_i) begin
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state_d = WAIT_REFILL_VALID;
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data_gnt_o = 1'b1;
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// if this was a write we still need to give a grant to the store unit
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if (mem_req_q.we)
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data_gnt_o = 1'b1;
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end
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if (miss_gnt_i && !mem_req_q.we)
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@ -317,8 +324,9 @@ module cache_ctrl #(
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if (data_req_i) begin
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// save index, be and we
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mem_req_d.index = address_index_i;
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mem_req_d.be = data_be_i;
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mem_req_d.we = data_we_i;
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mem_req_d.be = data_be_i;
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mem_req_d.size = data_size_i;
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mem_req_d.we = data_we_i;
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mem_req_d.wdata = data_wdata_i;
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mem_req_d.tag = address_tag_i;
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@ -48,6 +48,7 @@ module load_unit (
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output logic data_req_o,
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output logic data_we_o,
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output logic [7:0] data_be_o,
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output logic [1:0] data_size_o,
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output logic kill_req_o,
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output logic tag_valid_o,
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input logic data_gnt_i,
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@ -92,6 +93,7 @@ module load_unit (
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kill_req_o = 1'b0;
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tag_valid_o = 1'b0;
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data_be_o = lsu_ctrl_i.be;
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data_size_o = extract_transfer_size(lsu_ctrl_i.operator);
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pop_ld_o = 1'b0;
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case (CS)
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@ -133,6 +133,8 @@ module lsu #(
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logic [2:0][63:0] data_wdata_i;
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logic [2:0] data_req_i;
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logic [2:0] data_we_i;
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logic [2:0][1:0] data_size_i;
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logic [2:0] kill_req_i;
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logic [2:0] tag_valid_i;
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logic [2:0][7:0] data_be_i;
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@ -163,6 +165,7 @@ module lsu #(
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.data_req_i ( data_req_i ),
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.data_we_i ( data_we_i ),
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.data_be_i ( data_be_i ),
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.data_size_i ( data_size_i ),
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.kill_req_i ( kill_req_i ),
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.tag_valid_i ( tag_valid_i ),
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.data_gnt_o ( data_gnt_o ),
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@ -202,6 +205,7 @@ module lsu #(
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.data_req_o ( data_req_i [0] ),
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.data_we_o ( data_we_i [0] ),
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.data_be_o ( data_be_i [0] ),
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.data_size_o ( data_size_i [0] ),
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.kill_req_o ( kill_req_i [0] ),
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.tag_valid_o ( tag_valid_i [0] ),
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.data_gnt_i ( data_gnt_o [0] ),
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@ -237,6 +241,7 @@ module lsu #(
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.data_req_o ( data_req_i [2] ),
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.data_we_o ( data_we_i [2] ),
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.data_be_o ( data_be_i [2] ),
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.data_size_o ( data_size_i [2] ),
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.kill_req_o ( kill_req_i [2] ),
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.tag_valid_o ( tag_valid_i [2] ),
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.data_gnt_i ( data_gnt_o [2] ),
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@ -273,6 +278,7 @@ module lsu #(
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.data_req_o ( data_req_i [1] ),
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.data_we_o ( data_we_i [1] ),
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.data_be_o ( data_be_i [1] ),
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.data_size_o ( data_size_i [1] ),
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.kill_req_o ( kill_req_i [1] ),
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.tag_valid_o ( tag_valid_i [1] ),
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.data_gnt_i ( data_gnt_o [1] ),
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@ -57,6 +57,7 @@ module miss_handler #(
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logic [NR_PORTS-1:0][63:0] miss_req_wdata;
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logic [NR_PORTS-1:0] miss_req_we;
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logic [NR_PORTS-1:0][7:0] miss_req_be;
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logic [NR_PORTS-1:0][1:0] miss_req_size;
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// Cache Line Refill <-> AXI
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logic req_fsm_miss_valid;
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@ -340,17 +341,17 @@ module miss_handler #(
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// Bypass Arbiter
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// ----------------------
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// Connection Arbiter <-> AXI
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logic req_fsm_bypass_valid;
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logic [63:0] req_fsm_bypass_addr;
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logic [63:0] req_fsm_bypass_wdata;
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logic req_fsm_bypass_we;
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logic [7:0] req_fsm_bypass_be;
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logic gnt_bypass_fsm;
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logic valid_bypass_fsm;
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logic [63:0] data_bypass_fsm;
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logic [$clog2(NR_PORTS)-1:0] id_fsm_bypass;
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logic [AXI_ID_WIDTH-1:0] id_bypass_fsm;
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logic req_fsm_bypass_valid;
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logic [63:0] req_fsm_bypass_addr;
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logic [63:0] req_fsm_bypass_wdata;
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logic req_fsm_bypass_we;
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logic [7:0] req_fsm_bypass_be;
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logic [1:0] req_fsm_bypass_size;
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logic gnt_bypass_fsm;
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logic valid_bypass_fsm;
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logic [63:0] data_bypass_fsm;
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logic [$clog2(NR_PORTS)-1:0] id_fsm_bypass;
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logic [AXI_ID_WIDTH-1:0] id_bypass_fsm;
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arbiter #(
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.NR_PORTS ( NR_PORTS ),
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@ -362,6 +363,7 @@ module miss_handler #(
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.data_wdata_i ( miss_req_wdata ),
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.data_we_i ( miss_req_we ),
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.data_be_i ( miss_req_be ),
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.data_size_i ( miss_req_size ),
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.data_gnt_o ( bypass_gnt_o ),
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.data_rvalid_o ( bypass_valid_o ),
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.data_rdata_o ( bypass_data_o ),
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@ -373,6 +375,7 @@ module miss_handler #(
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.data_req_o ( req_fsm_bypass_valid ),
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.data_we_o ( req_fsm_bypass_we ),
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.data_be_o ( req_fsm_bypass_be ),
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.data_size_o ( req_fsm_bypass_size ),
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.data_gnt_i ( gnt_bypass_fsm ),
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.data_rvalid_i ( valid_bypass_fsm ),
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.data_rdata_i ( data_bypass_fsm ),
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@ -389,6 +392,7 @@ module miss_handler #(
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.we_i ( req_fsm_bypass_we ),
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.wdata_i ( req_fsm_bypass_wdata ),
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.be_i ( req_fsm_bypass_be ),
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.size_i ( req_fsm_bypass_size ),
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.id_i ( {{{AXI_ID_WIDTH-$clog2(NR_PORTS)}{1'b0}}, id_fsm_bypass} ),
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.valid_o ( valid_bypass_fsm ),
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.rdata_o ( data_bypass_fsm ),
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@ -412,6 +416,7 @@ module miss_handler #(
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.we_i ( req_fsm_miss_we ),
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.wdata_i ( req_fsm_miss_wdata ),
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.be_i ( req_fsm_miss_be ),
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.size_i ( 2'b11 ),
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.id_i ( '0 ),
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.valid_o ( valid_miss_fsm ),
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.rdata_o ( data_miss_fsm ),
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@ -445,6 +450,7 @@ module miss_handler #(
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miss_req_wdata [i] = miss_req.wdata;
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miss_req_we [i] = miss_req.we;
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miss_req_be [i] = miss_req.be;
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miss_req_size [i] = miss_req.size;
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end
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end
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@ -474,6 +480,7 @@ module arbiter #(
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input logic [NR_PORTS-1:0][DATA_WIDTH-1:0] data_wdata_i,
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input logic [NR_PORTS-1:0] data_we_i,
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input logic [NR_PORTS-1:0][DATA_WIDTH/8-1:0] data_be_i,
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input logic [NR_PORTS-1:0][1:0] data_size_i,
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output logic [NR_PORTS-1:0] data_gnt_o,
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output logic [NR_PORTS-1:0] data_rvalid_o,
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output logic [NR_PORTS-1:0][DATA_WIDTH-1:0] data_rdata_o,
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@ -485,6 +492,7 @@ module arbiter #(
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output logic [DATA_WIDTH-1:0] data_wdata_o,
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output logic data_we_o,
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output logic [DATA_WIDTH/8-1:0] data_be_o,
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output logic [1:0] data_size_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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input logic [DATA_WIDTH-1:0] data_rdata_i
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@ -511,6 +519,7 @@ module arbiter #(
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address_o = address_i[request_index];
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data_wdata_o = data_wdata_i[request_index];
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data_be_o = data_be_i[request_index];
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data_size_o = data_size_i[request_index];
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data_we_o = data_we_i[request_index];
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data_gnt_o[request_index] = data_gnt_i;
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id_o = request_index;
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@ -569,6 +578,7 @@ module axi_adapter #(
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input logic we_i,
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input logic [(DATA_WIDTH/64)-1:0][63:0] wdata_i,
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input logic [(DATA_WIDTH/64)-1:0][7:0] be_i,
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input logic [1:0] size_i,
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input logic [AXI_ID_WIDTH-1:0] id_i,
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// read port
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output logic valid_o,
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@ -603,7 +613,7 @@ module axi_adapter #(
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axi.aw_prot = 3'b0;
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axi.aw_region = 4'b0;
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axi.aw_len = 8'b0;
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axi.aw_size = 3'b011; // 8 bytes
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axi.aw_size = {1'b0, size_i};
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axi.aw_burst = (req_i == SINGLE_REQ) ? 2'b00 : 2'b01; // fixed size for single request and incremental transfer for everything else
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axi.aw_lock = 1'b0;
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axi.aw_cache = 4'b0;
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@ -618,7 +628,7 @@ module axi_adapter #(
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axi.ar_prot = 3'b0;
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axi.ar_region = 4'b0;
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axi.ar_len = 8'b0;
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axi.ar_size = 3'b011; // 8 bytes
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axi.ar_size = {1'b0, size_i}; // 8 bytes
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axi.ar_burst = (req_i == SINGLE_REQ) ? 2'b00 : (CRITICAL_WORD_FIRST ? 2'b10 : 2'b01); // wrapping transfer in case of a critical word first strategy
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axi.ar_lock = 1'b0;
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axi.ar_cache = 4'b0;
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@ -81,6 +81,7 @@ module mmu #(
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output logic data_req_o,
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output logic data_we_o,
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output logic [7:0] data_be_o,
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output logic [1:0] data_size_o,
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output logic kill_req_o,
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output logic tag_valid_o,
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input logic data_gnt_i,
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@ -42,6 +42,7 @@ module nbdcache (
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input logic [2:0] data_req_i,
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input logic [2:0] data_we_i,
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input logic [2:0][7:0] data_be_i,
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input logic [2:0][1:0] data_size_i,
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input logic [2:0] kill_req_i,
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input logic [2:0] tag_valid_i,
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output logic [2:0] data_gnt_o,
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@ -111,6 +112,7 @@ module nbdcache (
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.data_req_i ( data_req_i [i] ),
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.data_we_i ( data_we_i [i] ),
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.data_be_i ( data_be_i [i] ),
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.data_size_i ( data_size_i [i] ),
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.kill_req_i ( kill_req_i [i] ),
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.tag_valid_i ( tag_valid_i [i] ),
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.data_gnt_o ( data_gnt_o [i] ),
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@ -44,6 +44,7 @@ module ptw #(
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output logic data_req_o,
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output logic data_we_o,
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output logic [7:0] data_be_o,
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output logic [1:0] data_size_o,
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output logic kill_req_o,
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output logic tag_valid_o,
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input logic data_gnt_i,
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@ -154,6 +155,7 @@ module ptw #(
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tag_valid_n = 1'b0;
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data_req_o = 1'b0;
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data_be_o = 8'hFF;
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data_size_o = 2'b11;
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data_we_o = 1'b0;
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ptw_error_o = 1'b0;
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itlb_update_o = 1'b0;
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@ -37,6 +37,7 @@ module store_buffer (
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input logic [63:0] paddr_i, // physical address of store which needs to be placed in the queue
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input logic [63:0] data_i, // data which is placed in the queue
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input logic [7:0] be_i, // byte enable in
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input logic [1:0] data_size_i, // type of request we are making (e.g.: bytes to write)
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// D$ interface
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output logic [11:0] address_index_o,
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@ -45,6 +46,7 @@ module store_buffer (
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output logic data_req_o,
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output logic data_we_o,
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output logic [7:0] data_be_o,
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output logic [1:0] data_size_o,
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output logic kill_req_o,
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output logic tag_valid_o,
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input logic data_gnt_i,
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@ -63,6 +65,7 @@ module store_buffer (
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logic [63:0] address;
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logic [63:0] data;
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logic [7:0] be;
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logic [1:0] data_size;
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logic valid; // this entry is valid, we need this for checking if the address offset matches
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} speculative_queue_n [DEPTH_SPEC-1:0], speculative_queue_q [DEPTH_SPEC-1:0],
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commit_queue_n [DEPTH_COMMIT-1:0], commit_queue_q [DEPTH_COMMIT-1:0];
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@ -94,9 +97,10 @@ module store_buffer (
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// LSU interface
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// we are ready to accept a new entry and the input data is valid
|
||||
if (valid_i) begin
|
||||
speculative_queue_n[speculative_write_pointer_q].address = paddr_i;
|
||||
speculative_queue_n[speculative_write_pointer_q].data = data_i;
|
||||
speculative_queue_n[speculative_write_pointer_q].be = be_i;
|
||||
speculative_queue_n[speculative_write_pointer_q].address = paddr_i;
|
||||
speculative_queue_n[speculative_write_pointer_q].data = data_i;
|
||||
speculative_queue_n[speculative_write_pointer_q].be = be_i;
|
||||
speculative_queue_n[speculative_write_pointer_q].data_size = data_size_i;
|
||||
speculative_queue_n[speculative_write_pointer_q].valid = 1'b1;
|
||||
// advance the write pointer
|
||||
speculative_write_pointer_n = speculative_write_pointer_q + 1'b1;
|
||||
|
|
@ -137,6 +141,7 @@ module store_buffer (
|
|||
assign tag_valid_o = 1'b0;
|
||||
assign data_wdata_o = commit_queue_q[commit_read_pointer_q].data;
|
||||
assign data_be_o = commit_queue_q[commit_read_pointer_q].be;
|
||||
assign data_size_o = commit_queue_q[commit_read_pointer_q].data_size;
|
||||
// we will never kill a request in the store buffer since we already know that the translation is valid
|
||||
// e.g.: a kill request will only be necessary if we are not sure if the requested memory address will result in a TLB fault
|
||||
assign kill_req_o = 1'b0;
|
||||
|
|
|
|||
|
|
@ -51,6 +51,7 @@ module store_unit (
|
|||
output logic data_req_o,
|
||||
output logic data_we_o,
|
||||
output logic [7:0] data_be_o,
|
||||
output logic [1:0] data_size_o,
|
||||
output logic kill_req_o,
|
||||
output logic tag_valid_o,
|
||||
input logic data_gnt_i,
|
||||
|
|
@ -67,6 +68,7 @@ module store_unit (
|
|||
// keep the data and the byte enable for the second cycle (after address translation)
|
||||
logic [63:0] st_data_n, st_data_q;
|
||||
logic [7:0] st_be_n, st_be_q;
|
||||
logic [1:0] st_data_size_n, st_data_size_q;
|
||||
logic [TRANS_ID_BITS-1:0] trans_id_n, trans_id_q;
|
||||
|
||||
// output assignments
|
||||
|
|
@ -175,8 +177,10 @@ module store_unit (
|
|||
// -----------
|
||||
// re-align the write data to comply with the address offset
|
||||
always_comb begin
|
||||
st_be_n = lsu_ctrl_i.be;
|
||||
st_data_n = lsu_ctrl_i.data;
|
||||
st_be_n = lsu_ctrl_i.be;
|
||||
st_data_n = lsu_ctrl_i.data;
|
||||
st_data_size_n = extract_transfer_size(lsu_ctrl_i.operator);
|
||||
|
||||
case (lsu_ctrl_i.vaddr[2:0])
|
||||
3'b000: st_data_n = lsu_ctrl_i.data;
|
||||
3'b001: st_data_n = {lsu_ctrl_i.data[55:0], lsu_ctrl_i.data[63:56]};
|
||||
|
|
@ -196,6 +200,7 @@ module store_unit (
|
|||
.valid_i ( st_valid ),
|
||||
.data_i ( st_data_q ),
|
||||
.be_i ( st_be_q ),
|
||||
.data_size_i ( st_data_size_q ),
|
||||
// store buffer out
|
||||
.ready_o ( st_ready ),
|
||||
.*
|
||||
|
|
@ -205,15 +210,17 @@ module store_unit (
|
|||
// ---------------
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if(~rst_ni) begin
|
||||
CS <= IDLE;
|
||||
st_be_q <= '0;
|
||||
st_data_q <= '0;
|
||||
trans_id_q <= '0;
|
||||
CS <= IDLE;
|
||||
st_be_q <= '0;
|
||||
st_data_q <= '0;
|
||||
st_data_size_q <= '0;
|
||||
trans_id_q <= '0;
|
||||
end else begin
|
||||
CS <= NS;
|
||||
st_be_q <= st_be_n;
|
||||
st_data_q <= st_data_n;
|
||||
trans_id_q <= trans_id_n;
|
||||
CS <= NS;
|
||||
st_be_q <= st_be_n;
|
||||
st_data_q <= st_data_n;
|
||||
trans_id_q <= trans_id_n;
|
||||
st_data_size_q <= st_data_size_n;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue