Clean up irrelevant FIXME/TODO

core/alu.sv

@@ -130,7 +130,6 @@ module alu
   // Shifts
   // ---------
 
-  // TODO: this can probably optimized significantly
   logic                    shift_left;  // should we shift left
   logic                    shift_arithmetic;
 

core/branch_unit.sv

@@ -57,7 +57,7 @@ module branch_unit #(
   always_comb begin : mispredict_handler
     // set the jump base, for JALR we need to look at the register, for all other control flow instructions we can take the current PC
     automatic logic [CVA6Cfg.VLEN-1:0] jump_base;
-    // TODO(zarubaf): The ALU can be used to calculate the branch target
+    // IMPROVEMENT: The ALU can be used to calculate the branch target
     jump_base = (fu_data_i.operation == ariane_pkg::JALR) ? fu_data_i.operand_a[CVA6Cfg.VLEN-1:0] : pc_i;
 
     resolve_branch_o = 1'b0;
@@ -67,7 +67,7 @@ module branch_unit #(
     resolved_branch_o.is_mispredict = 1'b0;
     resolved_branch_o.cf_type = branch_predict_i.cf;
     // calculate next PC, depending on whether the instruction is compressed or not this may be different
-    // TODO(zarubaf): We already calculate this a couple of times, maybe re-use?
+    // IMPROVEMENT: We already calculate this a couple of times, maybe re-use?
     next_pc                          = pc_i + ((is_compressed_instr_i) ? {{CVA6Cfg.VLEN-2{1'b0}}, 2'h2} : {{CVA6Cfg.VLEN-3{1'b0}}, 3'h4});
     // calculate target address simple 64 bit addition
     target_address = $unsigned($signed(jump_base) + $signed(fu_data_i.imm[CVA6Cfg.VLEN-1:0]));

core/cvxif_fu.sv

@@ -66,8 +66,7 @@ module cvxif_fu
   always_comb begin
     x_exception_o.valid = x_illegal_i;
     x_exception_o.cause = x_illegal_i ? riscv::ILLEGAL_INSTR : '0;
-    if (CVA6Cfg.TvalEn)
-      x_exception_o.tval = x_off_instr_i;  // TODO Optimization : Set exception in IRO.
+    if (CVA6Cfg.TvalEn) x_exception_o.tval = x_off_instr_i;
   end
 
 endmodule

core/decoder.sv

@@ -825,7 +825,7 @@ module decoder
               2'b01:   illegal_instr = illegal_instr_non_bm & illegal_instr_zic;
               2'b10:   illegal_instr = illegal_instr_non_bm & illegal_instr_bm;
               2'b11:   illegal_instr = illegal_instr_non_bm & illegal_instr_bm & illegal_instr_zic;
-              default: ;  // TODO: Check that default case is not synthesized.
+              default: ;
             endcase
           end
         end

core/frontend/frontend.sv

@@ -703,7 +703,7 @@ module frontend
     // we can unconditionally do PC + 4 here
     // or if the commit stage is halted, just take the current pc of the
     // instruction in the commit stage
-    // TODO(zarubaf) This adder can at least be merged with the one in the csr_regfile stage
+    // IMPROVEMENT: This adder can at least be merged with the one in the csr_regfile stage
     if (set_pc_commit_i) begin
       npc_d = pc_commit_i + (halt_i ? '0 : {{CVA6Cfg.VLEN - 3{1'b0}}, 3'b100});
     end

core/frontend/instr_queue.sv

@@ -39,7 +39,7 @@
 // The instruction front-end will stop issuing instructions as soon as the
 // fifo is full. This will gate the logic if the processor is e.g.: halted
 //
-// TODO(zarubaf): The instruction queues can be reduced to 16 bit. Potentially
+// IMPROVEMENT: The instruction queues can be reduced to 16 bit. Potentially
 // the replay mechanism gets more complicated as it can be that a 32 bit instruction
 // can not be pushed at once.
 
@@ -338,7 +338,6 @@ module instr_queue
 
       // output mux select
       for (int unsigned i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin
-        // TODO handle fetch_entry_o[1] if superscalar
         if (idx_ds[0][i]) begin
           if (CVA6Cfg.NrPMPEntries != 0 && instr_data_out[i].ex == ariane_pkg::FE_INSTR_ACCESS_FAULT) begin
             fetch_entry_o[0].ex.cause = riscv::INSTR_ACCESS_FAULT;

core/id_stage.sv

@@ -423,7 +423,6 @@ module id_stage #(
       // Clear the valid flag if issue has acknowledged the instruction
       if (issue_instr_ack_i[0]) issue_n[0].valid = 1'b0;
 
-      // TODO: refaire
       // if we have a space in the register and the fetch is valid, go get it
       // or the issue stage is currently acknowledging an instruction, which means that we will have space
       // for a new instruction

core/include/ariane_pkg.sv

@@ -28,7 +28,7 @@
 /// moved out to favour a fully parameterizable core.
 package ariane_pkg;
 
-  // TODO: Slowly move those parameters to the new system.
+  // IMPROVEMENT: Slowly move those parameters to the new system.
   localparam BITS_SATURATION_COUNTER = 2;
 
   // depth of store-buffers, this needs to be a power of two

core/include/config_pkg.sv

@@ -171,7 +171,7 @@ package config_pkg;
     int unsigned                 AxiUserWidth;
     // AXI burst in write
     bit                          AxiBurstWriteEn;
-    // TODO
+    // Transaction ID
     int unsigned                 MemTidWidth;
     // Instruction cache size (in bytes)
     int unsigned                 IcacheByteSize;

core/include/cv32a60x_config_pkg.sv

@@ -106,7 +106,7 @@ package cva6_config_pkg;
       NrStorePipeRegs: int'(0),
       DcacheIdWidth: int'(1),
       ObiVersion: int'(config_pkg::OBI_V1_6),
-      PipelineOnly: bit'(1)  //FIXME
+      PipelineOnly: bit'(1)
   };
 
 endpackage

core/include/cv32a65x_config_pkg.sv

@@ -106,7 +106,7 @@ package cva6_config_pkg;
       NrStorePipeRegs: int'(0),
       DcacheIdWidth: int'(1),
       ObiVersion: int'(config_pkg::OBI_V1_6),
-      PipelineOnly: bit'(1)  //FIXME
+      PipelineOnly: bit'(1)
   };
 
 endpackage

core/issue_read_operands.sv

@@ -245,7 +245,6 @@ module issue_read_operands
     assign rs = {fu_data_n[0].operand_b, fu_data_n[0].operand_a};
   end
 
-  // TODO check only for 1st instruction ??
   // Allow a cvxif transaction if we WaW condition are ok.
   assign cvxif_req_allowed = (issue_instr_i[0].fu == CVXIF) && !stall_waw[0];
   assign cvxif_instruction_valid = !issue_instr_i[0].ex.valid && issue_instr_valid_i[0] && cvxif_req_allowed;