pmp: wire the full width of all signals

Certain synthesis tools do not support overflows with NrPMPEntries-1 if
NrPMPEntries=0. So in this commit we just wire up the entire PMP
configuration through all units (maximum number of PMP entries is 16).

src/ariane.sv

@@ -182,8 +182,8 @@ module ariane #(
   logic                     icache_en_csr;
   logic                     debug_mode;
   logic                     single_step_csr_commit;
-  riscv::pmpcfg_t [ArianeCfg.NrPMPEntries-1:0] pmpcfg;
-  logic [ArianeCfg.NrPMPEntries-1:0][53:0]     pmpaddr;
+  riscv::pmpcfg_t [15:0]    pmpcfg;
+  logic [15:0][53:0]        pmpaddr;
   // ----------------------------
   // Performance Counters <-> *
   // ----------------------------

src/csr_regfile.sv

@@ -85,8 +85,8 @@ module csr_regfile #(
     input  logic  [63:0]          perf_data_i,                // read data from performance counter module
     output logic                  perf_we_o,
     // PMPs
-    output riscv::pmpcfg_t [NrPMPEntries-1:0] pmpcfg_o,   // PMP configuration containing pmpcfg for max 16 PMPs
-    output logic [NrPMPEntries-1:0][53:0]     pmpaddr_o   // PMP addresses
+    output riscv::pmpcfg_t [15:0] pmpcfg_o,   // PMP configuration containing pmpcfg for max 16 PMPs
+    output logic [15:0][53:0]     pmpaddr_o   // PMP addresses
 );
     // internal signal to keep track of access exceptions
     logic        read_access_exception, update_access_exception, privilege_violation;
@@ -143,7 +143,7 @@ module csr_regfile #(
     logic [15:0][53:0]        pmpaddr_q,  pmpaddr_d;
 
 
-    assign pmpcfg_o = pmpcfg_q[NrPMPEntries-1:0];
+    assign pmpcfg_o = pmpcfg_q[15:0];
     assign pmpaddr_o = pmpaddr_q;
 
     riscv::fcsr_t fcsr_q, fcsr_d;

src/ex_stage.sv

@@ -101,8 +101,8 @@ module ex_stage #(
     output logic                                   itlb_miss_o,
     output logic                                   dtlb_miss_o,
     // PMPs
-    input  riscv::pmpcfg_t [ArianeCfg.NrPMPEntries-1:0]  pmpcfg_i,
-    input  logic[ArianeCfg.NrPMPEntries-1:0][53:0]       pmpaddr_i
+    input  riscv::pmpcfg_t [15:0]                  pmpcfg_i,
+    input  logic[15:0][53:0]                       pmpaddr_i
 );
 
     // -------------------------

src/load_store_unit.sv

@@ -68,8 +68,8 @@ module load_store_unit #(
     output amo_req_t                 amo_req_o,
     input  amo_resp_t                amo_resp_i,
     // PMP
-    input  riscv::pmpcfg_t [ArianeCfg.NrPMPEntries-1:0] pmpcfg_i,
-    input  logic [ArianeCfg.NrPMPEntries-1:0][53:0]     pmpaddr_i
+    input  riscv::pmpcfg_t [15:0]    pmpcfg_i,
+    input  logic [15:0][53:0]        pmpaddr_i
 );
     // data is misaligned
     logic data_misaligned;

src/mmu.sv

@@ -60,8 +60,8 @@ module mmu #(
     input  dcache_req_o_t                   req_port_i,
     output dcache_req_i_t                   req_port_o,
     // PMP
-    input  riscv::pmpcfg_t [ArianeCfg.NrPMPEntries-1:0] pmpcfg_i,
-    input  logic [ArianeCfg.NrPMPEntries-1:0][53:0]     pmpaddr_i
+    input  riscv::pmpcfg_t [15:0]           pmpcfg_i,
+    input  logic [15:0][53:0]               pmpaddr_i
 );
 
     logic                   iaccess_err;   // insufficient privilege to access this instruction page

src/pmp/src/pmp.sv

@@ -22,8 +22,8 @@ module pmp #(
     input riscv::pmp_access_t access_type_i,
     input riscv::priv_lvl_t priv_lvl_i,
     // Configuration
-    input logic [NR_ENTRIES-1:0][PMP_LEN-1:0] conf_addr_i,
-    input riscv::pmpcfg_t [NR_ENTRIES-1:0] conf_i,
+    input logic [15:0][PMP_LEN-1:0] conf_addr_i,
+    input riscv::pmpcfg_t [15:0] conf_i,
     // Output
     output logic allow_o
 );

src/ptw.sv

@@ -61,8 +61,9 @@ module ptw #(
     output logic                    itlb_miss_o,
     output logic                    dtlb_miss_o,
     // PMP
-    input  riscv::pmpcfg_t [ArianeCfg.NrPMPEntries-1:0]  pmpcfg_i,
-    input  logic [ArianeCfg.NrPMPEntries-1:0][53:0]      pmpaddr_i,
+
+    input  riscv::pmpcfg_t [15:0]   pmpcfg_i,
+    input  logic [15:0][53:0]       pmpaddr_i,
     output logic [riscv::PLEN-1:0]  bad_paddr_o
 
 );