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Fix bytewidth in bootrom axilite bridge (#1264)

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Dan Petrisko 2023-06-20 03:26:11 -07:00 • committed by GitHub
parent bcff0ec90b
commit 1b81b4865f
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corev_apu/openpiton/riscv_peripherals.sv
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@ -396,7 +396,7 @@ module riscv_peripherals #(
assign rom_rdata = (ariane_boot_sel_i) ? rom_rdata_bm : rom_rdata_linux;
noc_axilite_bridge #(
.SLAVE_RESP_BYTEWIDTH ( 8 ),
.SLAVE_RESP_BYTEWIDTH ( 0 ),
.SWAP_ENDIANESS ( SwapEndianess )
) i_bootrom_axilite_bridge (
.clk ( clk_i ),