mirror of
https://github.com/openhwgroup/cva6.git
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Connect the new AXI agent with CVA6 (#2182)
This commit is contained in:
AEzzejjari
GitHub
parent
ba6262a65c
commit
1c828c0a16
7 changed files with 208 additions and 172 deletions
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@ -1 +1 @@
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Subproject commit 4a70806f3cd8ddb5d693f4bfb99d16a4fbd2a15e
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Subproject commit b92d30f4d3f4f5f50056e5267a03d02a66b7b6da
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87
verif/env/uvme/cov/uvme_axi_covg.sv
vendored
87
verif/env/uvme/cov/uvme_axi_covg.sv
vendored
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@ -22,25 +22,25 @@ covergroup cg_axi_w_channel(string name)
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option.per_instance = 1;
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option.name = name;
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awready_to_valid: coverpoint (item.aw_delay) {
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awready_to_valid: coverpoint (item.ready_delay_cycle_chan_ax) {
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bins dly[] = {[0:16]};
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}
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wready_to_valid: coverpoint (item.w_data_trs[0].w_delay) {
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wready_to_valid: coverpoint (item.ready_delay_cycle_chan_w[0]) {
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bins dly[] = {[0:16]};
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}
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awsize: coverpoint (item.aw_size){
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awsize: coverpoint (item.m_size){
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bins size[] = {[0:3]};
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ignore_bins IGN_SIZE3 = {3} iff(uvme_cva6_pkg::XLEN == 32);
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}
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awlock: coverpoint (item.aw_lock){
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awlock: coverpoint (item.m_lock){
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bins lock[] = {[0:1]};
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ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA);
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}
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wstrb: coverpoint (item.w_data_trs[0].w_strb) {
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wstrb: coverpoint (item.m_wstrb[0]) {
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bins strb1 = {1};
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bins strb2 = {2};
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bins strb3 = {3};
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@ -72,12 +72,12 @@ covergroup cg_axi_b_channel(string name)
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option.per_instance = 1;
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option.name = name;
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bid: coverpoint (item.b_id){
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bid: coverpoint (item.m_id){
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bins one = {[1:3]} iff(!hpdcache);
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illegal_bins ILLEGAL_BINS = {2} iff(!hpdcache);
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ignore_bins IGN_EXID = {3} iff(!RVA && !hpdcache);
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}
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bresp: coverpoint (item.b_resp){
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bresp: coverpoint (item.m_resp[0]){
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bins zero = {0};
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bins one = {1};
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bins two = {2};
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@ -93,23 +93,23 @@ covergroup cg_axi_ar_channel(string name)
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option.per_instance = 1;
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option.name = name;
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arid: coverpoint (item.ar_id) {
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arid: coverpoint (item.m_id) {
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bins ID[] = {[0:1]} iff(!hpdcache);
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}
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arlen: coverpoint (item.ar_len) {
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arlen: coverpoint (item.m_len) {
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bins LEN[] = {[0:1]};
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}
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arsize: coverpoint (item.ar_size) {
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bins SIZE[] = {[0:3]} iff(item.ar_len == 0);
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arsize: coverpoint (item.m_size) {
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bins SIZE[] = {[0:3]} iff(item.m_len == 0);
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}
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arready_to_valid: coverpoint (item.ar_delay) {
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arready_to_valid: coverpoint (item.ready_delay_cycle_chan_ax) {
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bins dly[] = {[0:16]};
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}
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arlock: coverpoint (item.ar_lock){
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arlock: coverpoint (item.m_lock){
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bins lock[] = {[0:1]};
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ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA);
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}
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@ -136,15 +136,15 @@ covergroup cg_axi_r_channel(string name)
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option.per_instance = 1;
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option.name = name;
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rid: coverpoint (item.r_data_trs[index].r_id) {
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rid: coverpoint (item.m_id) {
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bins ID[] = {[0:3]} iff(!hpdcache);
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illegal_bins ILLEGAL_BINS = {2} iff(!hpdcache);
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ignore_bins IGN_EXID = {3} iff(!RVA && !hpdcache);
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}
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rlast: coverpoint (item.r_data_trs[index].r_last);
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rlast: coverpoint (item.m_last[index]);
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rresp: coverpoint (item.r_data_trs[index].r_resp){
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rresp: coverpoint (item.m_resp[index]){
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bins zero = {0};
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bins one = {1};
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bins two = {2};
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@ -168,7 +168,10 @@ class uvme_axi_covg_c extends uvm_component;
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bit HPDCache;
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// TLM
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_resp_fifo;
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_aw_req_fifo;
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_b_resp_fifo;
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_ar_req_fifo;
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_r_resp_fifo;
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// Covergroup instances
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cg_axi_w_channel w_axi_cg;
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@ -229,7 +232,10 @@ function void uvme_axi_covg_c::build_phase(uvm_phase phase);
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RVA = cfg.ext_a_supported;
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HPDCache = cfg.HPDCache_supported;
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uvme_axi_cov_resp_fifo = new("uvme_axi_cov_resp_fifo" , this);
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uvme_axi_cov_b_resp_fifo = new("uvme_axi_cov_b_resp_fifo" , this);
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uvme_axi_cov_r_resp_fifo = new("uvme_axi_cov_r_resp_fifo" , this);
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uvme_axi_cov_ar_req_fifo = new("uvme_axi_cov_ar_req_fifo" , this);
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uvme_axi_cov_aw_req_fifo = new("uvme_axi_cov_aw_req_fifo" , this);
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w_axi_cg = new("w_axi_cg");
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b_axi_cg = new("b_axi_cg");
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@ -244,25 +250,40 @@ task uvme_axi_covg_c::run_phase(uvm_phase phase);
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`uvm_info(get_type_name(), $sformatf("cov_model_enabled = %d", cfg.cov_model_enabled), UVM_HIGH)
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`uvm_info(get_type_name(), $sformatf("ATOMIC ENABLE = %d", RVA), UVM_HIGH)
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forever begin
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uvma_axi_transaction_c resp_item;
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uvma_axi_transaction_c aw_item;
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uvma_axi_transaction_c b_item;
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uvma_axi_transaction_c ar_item;
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uvma_axi_transaction_c r_item;
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uvme_axi_cov_resp_fifo.get(resp_item);
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case (resp_item.access_type)
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UVMA_AXI_ACCESS_WRITE : begin
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fork
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uvme_axi_cov_b_resp_fifo.get(b_item);
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uvme_axi_cov_r_resp_fifo.get(r_item);
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uvme_axi_cov_ar_req_fifo.get(ar_item);
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uvme_axi_cov_aw_req_fifo.get(aw_item);
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join_any
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disable fork;
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w_axi_cg.sample(resp_item, RVA);
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b_axi_cg.sample(resp_item, RVA, HPDCache);
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if(aw_item != null) begin
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`uvm_info(get_type_name(), $sformatf("WRITE REQ ITEM DETECTED"), UVM_LOW)
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w_axi_cg.sample(aw_item, RVA);
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end
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if(b_item != null) begin
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`uvm_info(get_type_name(), $sformatf("WRITE RESP ITEM DETECTED"), UVM_LOW)
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b_axi_cg.sample(b_item, RVA, HPDCache);
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end
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if(ar_item != null) begin
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`uvm_info(get_type_name(), $sformatf("READ ADDRESS ITEM DETECTED"), UVM_LOW)
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ar_axi_cg.sample(ar_item, RVA, HPDCache);
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end
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if(r_item != null) begin
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`uvm_info(get_type_name(), $sformatf("READ DATA ITEM DETECTED"), UVM_LOW)
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for(int i = 0; i <= r_item.m_len; i++) begin
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r_axi_cg.sample(r_item, i, RVA, HPDCache);
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end
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UVMA_AXI_ACCESS_READ : begin
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ar_axi_cg.sample(resp_item, RVA, HPDCache);
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for(int i = 0; i <= resp_item.ar_len; i++) begin
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r_axi_cg.sample(resp_item, i, RVA, HPDCache);
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end
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end
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endcase
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end
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end
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261
verif/env/uvme/cov/uvme_axi_ext_covg.sv
vendored
261
verif/env/uvme/cov/uvme_axi_ext_covg.sv
vendored
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@ -17,7 +17,7 @@
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*/
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covergroup cg_axi_aw_order(string name)
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with function sample(uvma_axi_transaction_c item[], int t_b1_to_aw, int t_w1_to_aw, bit RVA);
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with function sample(int t_b1_to_aw, int t_w1_to_aw);
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option.per_instance = 1;
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option.name = name;
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@ -27,21 +27,10 @@ covergroup cg_axi_aw_order(string name)
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bins outstanding = {1};
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}
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awlock1: coverpoint (item[0].aw_lock){
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bins lock[] = {[0:1]};
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ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA);
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}
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awlock2: coverpoint (item[1].aw_lock){
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bins lock[] = {[0:1]};
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ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA);
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}
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aw_axi_cross: cross outstanding_resp, awlock1, awlock2;
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endgroup : cg_axi_aw_order
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covergroup cg_axi_ar_order(string name)
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with function sample(uvma_axi_transaction_c item[], int t_r1_to_ar, int t_r1l_to_ar, int t_r1_to_r2, int t_r1l_to_r2l, bit RVA);
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with function sample(uvma_axi_transaction_c item[], int t_r1_to_ar, int t_r1l_to_ar, int t_r1_to_r2, int t_r1l_to_r2l);
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option.per_instance = 1;
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option.name = name;
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@ -57,57 +46,47 @@ covergroup cg_axi_ar_order(string name)
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}
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outoforder_resp_id0: coverpoint (t_r1_to_r2 < 0){
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bins normal = {0} iff(item[0].ar_id == 0);
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bins outoforder = {1} iff(item[0].ar_id == 0);
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bins normal = {0} iff(item[0].m_id == 0);
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bins outoforder = {1} iff(item[0].m_id == 0);
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}
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outoforder_resp_id1: coverpoint (t_r1_to_r2 < 0){
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bins normal = {0} iff(item[0].ar_id == 1);
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bins outoforder = {1} iff(item[0].ar_id == 1);
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bins normal = {0} iff(item[0].m_id == 1);
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bins outoforder = {1} iff(item[0].m_id == 1);
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}
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outoforder_last_resp_id0: coverpoint (t_r1l_to_r2l < 0){
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bins normal = {0} iff(item[0].ar_id == 0);
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bins outoforder = {1} iff(item[0].ar_id == 0);
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bins normal = {0} iff(item[0].m_id == 0);
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bins outoforder = {1} iff(item[0].m_id == 0);
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}
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outoforder_last_resp_id1: coverpoint (t_r1l_to_r2l < 0){
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bins normal = {0} iff(item[0].ar_id == 1);
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bins outoforder = {1} iff(item[0].ar_id == 1);
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bins normal = {0} iff(item[0].m_id == 1);
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bins outoforder = {1} iff(item[0].m_id == 1);
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}
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arid1: coverpoint (item[0].ar_id){
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arid1: coverpoint (item[0].m_id){
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bins id[] = {[0:1]};
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}
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arlen1: coverpoint (item[0].ar_len){
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arlen1: coverpoint (item[0].m_len){
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bins len[] = {[0:1]};
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}
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arlock1: coverpoint (item[0].ar_lock){
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bins lock[] = {[0:1]};
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ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA);
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}
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arid2: coverpoint (item[1].ar_id){
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arid2: coverpoint (item[1].m_id){
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bins id[] = {[0:1]};
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}
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arlen2: coverpoint (item[1].ar_len){
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arlen2: coverpoint (item[1].m_len){
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bins len[] = {[0:1]};
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}
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arlock2: coverpoint (item[1].ar_lock){
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bins lock[] = {[0:1]};
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ignore_bins IGN_EXCLUSIVE = {1} iff(!RVA);
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}
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ar_axi_outstanding_cross: cross outstanding_resp, outstanding_last_resp, arid1, arlen1, arlock1, arid2, arlen2, arlock2{
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ar_axi_outstanding_cross: cross outstanding_resp, outstanding_last_resp, arid1, arlen1, arid2, arlen2{
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ignore_bins IGN_CROSS1 = binsof(outstanding_resp) intersect{1} &&
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binsof(outstanding_last_resp) intersect{1};
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}
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aw_axi_outoforder_id0_cross: cross outoforder_resp_id0, outoforder_last_resp_id0, arlen1, arlock1, arlen2, arlock2{
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aw_axi_outoforder_id0_cross: cross outoforder_resp_id0, outoforder_last_resp_id0, arlen1, arlen2{
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ignore_bins IGN_CROSS1 = binsof(outoforder_resp_id0) intersect{1} &&
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binsof(outoforder_last_resp_id0) intersect{0} &&
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binsof(arlen2) intersect{0};
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@ -116,7 +95,7 @@ covergroup cg_axi_ar_order(string name)
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binsof(arlen1) intersect{0};
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}
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aw_axi_outoforder_id1_cross: cross outoforder_resp_id1, outoforder_last_resp_id1, arlen1, arlock1, arlen2, arlock2{
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aw_axi_outoforder_id1_cross: cross outoforder_resp_id1, outoforder_last_resp_id1, arlen1, arlen2{
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ignore_bins IGN_CROSS1 = binsof(outoforder_resp_id1) intersect{1} &&
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binsof(outoforder_last_resp_id1) intersect{0} &&
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binsof(arlen2) intersect{0};
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@ -131,11 +110,6 @@ endgroup : cg_axi_ar_order
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*/
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class uvme_axi_ext_covg_c extends uvm_component;
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// Objects
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uvme_cva6_cntxt_c cntxt;
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uvme_cva6_cfg_c cfg;
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bit RVA;
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// Time between write transfer
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int t_b1_to_aw; // <0 (outstanding)
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int t_w1_to_aw; // <0 (outstanding)
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@ -145,6 +119,9 @@ class uvme_axi_ext_covg_c extends uvm_component;
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int t_r1l_to_ar; // <0 (outstanding)
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int t_r1_to_r2; // <0 (r2 run before r1)
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int t_r1l_to_r2l; // <0 (last r2 run before last r1)
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int write_resp_status = 0;
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int read_resp_status = 0;
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// Covergroup instances
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cg_axi_aw_order aw_axi_order_cg;
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@ -154,10 +131,11 @@ class uvme_axi_ext_covg_c extends uvm_component;
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uvma_axi_transaction_c aw_trs_fifo[];
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uvma_axi_transaction_c ar_trs_fifo[];
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int order_resp;
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// TLM
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_fifo;
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_aw_req_fifo;
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_b_resp_fifo;
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_ar_req_fifo;
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uvm_tlm_analysis_fifo #(uvma_axi_transaction_c) uvme_axi_cov_r_resp_fifo;
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`uvm_component_utils_begin(uvme_axi_ext_covg_c)
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`uvm_component_utils_end
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@ -168,8 +146,7 @@ class uvme_axi_ext_covg_c extends uvm_component;
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extern function new(string name="uvme_axi_ext_covg", uvm_component parent=null);
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/**
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* 1. Ensures cfg & cntxt handles are not null.
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* 2. Builds fifos.
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* Builds fifos.
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*/
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extern virtual function void build_phase(uvm_phase phase);
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@ -179,14 +156,34 @@ class uvme_axi_ext_covg_c extends uvm_component;
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extern virtual task run_phase(uvm_phase phase);
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/**
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* Forks all sampling loops
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* get transaction from monitor
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*/
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extern virtual function int aw_time_operations();
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extern virtual task get_ar_item();
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/**
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* get transaction from monitor
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*/
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extern virtual task get_r_item();
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/**
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* get transaction from monitor
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*/
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extern virtual task get_aw_item();
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/**
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* get transaction from monitor
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*/
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extern virtual task get_b_item();
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/**
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* Forks all sampling loops
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*/
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extern virtual function int ar_time_operations();
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extern virtual function void aw_time_operations();
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/**
|
||||
* Forks all sampling loops
|
||||
*/
|
||||
extern virtual function void ar_time_operations();
|
||||
|
||||
endclass : uvme_axi_ext_covg_c
|
||||
|
||||
|
|
@ -201,22 +198,13 @@ function void uvme_axi_ext_covg_c::build_phase(uvm_phase phase);
|
|||
|
||||
super.build_phase(phase);
|
||||
|
||||
void'(uvm_config_db#(uvme_cva6_cfg_c)::get(this, "", "cfg", cfg));
|
||||
if (cfg == null) begin
|
||||
`uvm_fatal("cfg", "Context handle is null")
|
||||
end
|
||||
|
||||
void'(uvm_config_db#(uvme_cva6_cntxt_c)::get(this, "", "cntxt", cntxt));
|
||||
if (cntxt == null) begin
|
||||
`uvm_fatal("CNTXT", "Context handle is null")
|
||||
end
|
||||
|
||||
RVA = cfg.ext_a_supported;
|
||||
|
||||
aw_axi_order_cg = new("aw_axi_order_cg");
|
||||
ar_axi_order_cg = new("ar_axi_order_cg");
|
||||
|
||||
uvme_axi_cov_fifo = new("uvme_axi_cov_fifo" , this);
|
||||
uvme_axi_cov_b_resp_fifo = new("uvme_axi_cov_b_resp_fifo" , this);
|
||||
uvme_axi_cov_r_resp_fifo = new("uvme_axi_cov_r_resp_fifo" , this);
|
||||
uvme_axi_cov_ar_req_fifo = new("uvme_axi_cov_ar_req_fifo" , this);
|
||||
uvme_axi_cov_aw_req_fifo = new("uvme_axi_cov_aw_req_fifo" , this);
|
||||
|
||||
endfunction : build_phase
|
||||
|
||||
|
|
@ -224,82 +212,109 @@ task uvme_axi_ext_covg_c::run_phase(uvm_phase phase);
|
|||
|
||||
super.run_phase(phase);
|
||||
forever begin
|
||||
uvma_axi_transaction_c resp_item;
|
||||
|
||||
uvme_axi_cov_fifo.get(resp_item);
|
||||
case (resp_item.access_type)
|
||||
fork
|
||||
get_aw_item();
|
||||
get_b_item();
|
||||
get_ar_item();
|
||||
get_r_item();
|
||||
join_any
|
||||
|
||||
if(aw_trs_fifo.size() == 2 && write_resp_status == 2) begin
|
||||
aw_time_operations();
|
||||
aw_axi_order_cg.sample(t_b1_to_aw, t_w1_to_aw);
|
||||
aw_trs_fifo = new [aw_trs_fifo.size()-1] (aw_trs_fifo);
|
||||
write_resp_status--;
|
||||
end
|
||||
|
||||
UVMA_AXI_ACCESS_WRITE : begin
|
||||
|
||||
aw_trs_fifo = new [aw_trs_fifo.size()+1] (aw_trs_fifo);
|
||||
aw_trs_fifo[aw_trs_fifo.size()-1] = new resp_item;
|
||||
if(aw_trs_fifo.size() == 2) begin
|
||||
order_resp = aw_time_operations();
|
||||
aw_axi_order_cg.sample(aw_trs_fifo, t_b1_to_aw, t_w1_to_aw, RVA);
|
||||
if(order_resp == 1) aw_trs_fifo[0] = new aw_trs_fifo[1];
|
||||
aw_trs_fifo = new [aw_trs_fifo.size()-1] (aw_trs_fifo);
|
||||
end
|
||||
|
||||
end
|
||||
UVMA_AXI_ACCESS_READ : begin
|
||||
|
||||
ar_trs_fifo = new [ar_trs_fifo.size()+1] (ar_trs_fifo);
|
||||
ar_trs_fifo[ar_trs_fifo.size()-1] = new resp_item;
|
||||
|
||||
if(ar_trs_fifo.size() == 2) begin
|
||||
|
||||
order_resp = ar_time_operations();
|
||||
ar_axi_order_cg.sample(ar_trs_fifo, t_r1_to_ar, t_r1l_to_ar, t_r1_to_r2, t_r1l_to_r2l, RVA);
|
||||
if(order_resp == 1) ar_trs_fifo[0] = new ar_trs_fifo[1];
|
||||
ar_trs_fifo = new [ar_trs_fifo.size()-1] (ar_trs_fifo);
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
endcase
|
||||
if(ar_trs_fifo.size() == 2 && read_resp_status == 2) begin
|
||||
ar_time_operations();
|
||||
ar_axi_order_cg.sample(ar_trs_fifo, t_r1_to_ar, t_r1l_to_ar, t_r1_to_r2, t_r1l_to_r2l);
|
||||
ar_trs_fifo = new [ar_trs_fifo.size()-1] (ar_trs_fifo);
|
||||
read_resp_status--;
|
||||
end
|
||||
|
||||
disable fork;
|
||||
end
|
||||
|
||||
endtask : run_phase
|
||||
|
||||
function int uvme_axi_ext_covg_c::ar_time_operations();
|
||||
int order_resp = 1;
|
||||
uvma_axi_transaction_c axi_transaction;
|
||||
|
||||
if(ar_trs_fifo[0].ar_start_time > ar_trs_fifo[1].ar_start_time) begin
|
||||
task uvme_axi_ext_covg_c::get_aw_item();
|
||||
|
||||
axi_transaction = new ar_trs_fifo[0];
|
||||
ar_trs_fifo[0] = new ar_trs_fifo[1];
|
||||
ar_trs_fifo[1] = new axi_transaction;
|
||||
order_resp = 0;
|
||||
uvma_axi_transaction_c aw_item;
|
||||
uvme_axi_cov_aw_req_fifo.get(aw_item);
|
||||
`uvm_info(get_type_name(), $sformatf("WRITE REQ ITEM DETECTED"), UVM_LOW)
|
||||
aw_trs_fifo = new [aw_trs_fifo.size()+1] (aw_trs_fifo);
|
||||
aw_trs_fifo[aw_trs_fifo.size()-1] = new aw_item;
|
||||
|
||||
endtask : get_aw_item
|
||||
|
||||
|
||||
task uvme_axi_ext_covg_c::get_ar_item();
|
||||
|
||||
uvma_axi_transaction_c ar_item;
|
||||
uvme_axi_cov_ar_req_fifo.get(ar_item);
|
||||
`uvm_info(get_type_name(), $sformatf("READ REQ ITEM DETECTED"), UVM_LOW)
|
||||
ar_trs_fifo = new [ar_trs_fifo.size()+1] (ar_trs_fifo);
|
||||
ar_trs_fifo[ar_trs_fifo.size()-1] = new ar_item;
|
||||
|
||||
endtask : get_ar_item
|
||||
|
||||
|
||||
task uvme_axi_ext_covg_c::get_b_item();
|
||||
|
||||
uvma_axi_transaction_c b_item;
|
||||
uvme_axi_cov_b_resp_fifo.get(b_item);
|
||||
`uvm_info(get_type_name(), $sformatf("WRITE RESP ITEM DETECTED"), UVM_LOW)
|
||||
foreach(aw_trs_fifo[i]) begin
|
||||
if (aw_trs_fifo[i].m_id == b_item.m_id) begin
|
||||
aw_trs_fifo[i].m_resp = b_item.m_resp;
|
||||
aw_trs_fifo[i].m_timestamp_b = b_item.m_timestamp_b;
|
||||
aw_trs_fifo = new [aw_trs_fifo.size()+1] (aw_trs_fifo);
|
||||
aw_trs_fifo[aw_trs_fifo.size()-1] = new aw_trs_fifo[i];
|
||||
write_resp_status++;
|
||||
break;
|
||||
end
|
||||
end
|
||||
|
||||
t_r1_to_ar = ar_trs_fifo[1].ar_start_time - ar_trs_fifo[0].r_data_trs[0].r_start_time;
|
||||
t_r1l_to_ar = ar_trs_fifo[1].ar_start_time - ar_trs_fifo[0].r_data_trs[ar_trs_fifo[0].r_data_trs.size()-1].r_start_time;
|
||||
t_r1_to_r2 = ar_trs_fifo[1].r_data_trs[0].r_start_time - ar_trs_fifo[0].r_data_trs[0].r_start_time;
|
||||
t_r1l_to_r2l = ar_trs_fifo[1].r_data_trs[ar_trs_fifo[1].r_data_trs.size()-1].r_start_time - ar_trs_fifo[0].r_data_trs[ar_trs_fifo[0].r_data_trs.size()-1].r_start_time;
|
||||
endtask : get_b_item
|
||||
|
||||
return order_resp;
|
||||
|
||||
task uvme_axi_ext_covg_c::get_r_item();
|
||||
|
||||
uvma_axi_transaction_c r_item;
|
||||
uvme_axi_cov_r_resp_fifo.get(r_item);
|
||||
`uvm_info(get_type_name(), $sformatf("READ RESP ITEM DETECTED"), UVM_LOW)
|
||||
foreach(ar_trs_fifo[i]) begin
|
||||
if (ar_trs_fifo[i].m_id == r_item.m_id) begin
|
||||
ar_trs_fifo[i].m_resp.push_back(r_item.m_resp[0]);
|
||||
ar_trs_fifo[i].m_data.push_back(r_item.m_data[0]);
|
||||
ar_trs_fifo[i].m_timestamp_x.push_back(r_item.m_timestamp_x[0]);
|
||||
ar_trs_fifo = new [ar_trs_fifo.size()+1] (ar_trs_fifo);
|
||||
ar_trs_fifo[ar_trs_fifo.size()-1] = new ar_trs_fifo[i];
|
||||
read_resp_status++;
|
||||
break;
|
||||
end
|
||||
end
|
||||
|
||||
endtask : get_r_item
|
||||
|
||||
|
||||
function void uvme_axi_ext_covg_c::ar_time_operations();
|
||||
|
||||
t_r1_to_ar = ar_trs_fifo[1].m_timestamp_ax - ar_trs_fifo[0].m_timestamp_x[0];
|
||||
t_r1l_to_ar = ar_trs_fifo[1].m_timestamp_ax - ar_trs_fifo[0].m_timestamp_x[ar_trs_fifo[0].m_timestamp_x.size()-1];
|
||||
t_r1_to_r2 = ar_trs_fifo[1].m_timestamp_x[0] - ar_trs_fifo[0].m_timestamp_x[0];
|
||||
t_r1l_to_r2l = ar_trs_fifo[1].m_timestamp_x[ar_trs_fifo[1].m_timestamp_x.size()-1] - ar_trs_fifo[0].m_timestamp_x[ar_trs_fifo[0].m_timestamp_x.size()-1];
|
||||
|
||||
endfunction : ar_time_operations
|
||||
|
||||
function int uvme_axi_ext_covg_c::aw_time_operations();
|
||||
int order_resp = 1;
|
||||
uvma_axi_transaction_c axi_transaction;
|
||||
|
||||
if(aw_trs_fifo[0].aw_start_time > aw_trs_fifo[1].aw_start_time) begin
|
||||
function void uvme_axi_ext_covg_c::aw_time_operations();
|
||||
|
||||
axi_transaction = new aw_trs_fifo[0];
|
||||
aw_trs_fifo[0] = new aw_trs_fifo[1];
|
||||
aw_trs_fifo[1] = new axi_transaction;
|
||||
order_resp = 0;
|
||||
|
||||
end
|
||||
|
||||
t_b1_to_aw = aw_trs_fifo[1].aw_start_time - aw_trs_fifo[0].b_start_time;
|
||||
t_w1_to_aw = aw_trs_fifo[1].aw_start_time - aw_trs_fifo[0].w_data_trs[0].w_start_time;
|
||||
|
||||
return order_resp;
|
||||
t_b1_to_aw = aw_trs_fifo[1].m_timestamp_ax - aw_trs_fifo[0].m_timestamp_b;
|
||||
t_w1_to_aw = aw_trs_fifo[1].m_timestamp_ax - aw_trs_fifo[0].m_timestamp_x[0];
|
||||
|
||||
endfunction : aw_time_operations
|
||||
|
||||
|
|
|
|||
1
verif/env/uvme/uvme_cva6_cfg.sv
vendored
1
verif/env/uvme/uvme_cva6_cfg.sv
vendored
|
|
@ -188,6 +188,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
|
|||
isacov_cfg.reg_hazards_enabled == 1;
|
||||
rvfi_cfg.nret == CVA6Cfg.NrCommitPorts;
|
||||
unified_traps == 0;
|
||||
axi_cfg.rand_channel_delay_enabled == 0;
|
||||
|
||||
if (is_active == UVM_ACTIVE) {
|
||||
clknrst_cfg.is_active == UVM_ACTIVE;
|
||||
|
|
|
|||
11
verif/env/uvme/uvme_cva6_env.sv
vendored
11
verif/env/uvme/uvme_cva6_env.sv
vendored
|
|
@ -395,8 +395,15 @@ function void uvme_cva6_env_c::connect_coverage_model();
|
|||
rvfi_agent.rvfi_core_ap.connect(isacov_agent.monitor.rvfi_instr_imp);
|
||||
|
||||
if(cfg.axi_cfg.cov_model_enabled) begin
|
||||
axi_agent.vsequencer.synchronizer.uvma_sqr_trs_port.connect(cov_model.axi_covg.uvme_axi_cov_resp_fifo.analysis_export);
|
||||
axi_agent.vsequencer.synchronizer.uvma_sqr_trs_port.connect(cov_model.axi_ext_covg.uvme_axi_cov_fifo.analysis_export);
|
||||
axi_agent.monitor.m_axi_superset_write_rsp_packets_collected.connect(cov_model.axi_covg.uvme_axi_cov_b_resp_fifo.analysis_export);
|
||||
axi_agent.monitor.m_axi_superset_read_rsp_packets_collected .connect(cov_model.axi_covg.uvme_axi_cov_r_resp_fifo.analysis_export);
|
||||
axi_agent.monitor.m_axi_superset_read_req_packets_collected .connect(cov_model.axi_covg.uvme_axi_cov_ar_req_fifo.analysis_export);
|
||||
axi_agent.monitor.m_axi_superset_write_req_packets_collected.connect(cov_model.axi_covg.uvme_axi_cov_aw_req_fifo.analysis_export);
|
||||
|
||||
axi_agent.monitor.m_axi_superset_write_rsp_packets_collected.connect(cov_model.axi_ext_covg.uvme_axi_cov_b_resp_fifo.analysis_export);
|
||||
axi_agent.monitor.m_axi_superset_read_rsp_packets_collected . connect(cov_model.axi_ext_covg.uvme_axi_cov_r_resp_fifo.analysis_export);
|
||||
axi_agent.monitor.m_axi_superset_read_req_packets_collected .connect(cov_model.axi_ext_covg.uvme_axi_cov_ar_req_fifo.analysis_export);
|
||||
axi_agent.monitor.m_axi_superset_write_req_packets_collected.connect(cov_model.axi_ext_covg.uvme_axi_cov_aw_req_fifo.analysis_export);
|
||||
end
|
||||
|
||||
endfunction: connect_coverage_model
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
`include "uvmt_axi_switch_intf.sv"
|
||||
`include "uvmt_default_inputs_intf.sv"
|
||||
`include "uvma_axi_intf.sv"
|
||||
|
||||
/**
|
||||
* Encapsulates all the types and test cases for the verification of an
|
||||
|
|
|
|||
|
|
@ -241,26 +241,17 @@ function void uvmt_cva6_base_test_c::build_phase(uvm_phase phase);
|
|||
create_env ();
|
||||
create_components();
|
||||
|
||||
`uvm_info("BASE TEST", $sformatf("AXI config version = %s", env_cfg.axi_cfg.version), UVM_LOW)
|
||||
|
||||
factory = uvm_factory::get();
|
||||
|
||||
case (env_cfg.axi_cfg.version)
|
||||
UVMA_AXI_VERSION_1P2 : begin
|
||||
factory.set_type_override_by_name("uvma_axi_synchronizer_c", "uvma_axi_ext_synchronizer_c");
|
||||
`uvm_info("BASE TEST", $sformatf("AXI EXT SYNCHRONIZER"), UVM_LOW)
|
||||
end
|
||||
UVMA_AXI_VERSION_1P3 : begin
|
||||
factory.set_type_override_by_name("uvma_axi_synchronizer_c", "uvma_axi_amo_synchronizer_c");
|
||||
`uvm_info("BASE TEST", $sformatf("AXI AMO SYNCHRONIZER"), UVM_LOW)
|
||||
end
|
||||
endcase
|
||||
if(env_cfg.axi_cfg.version == 1) begin
|
||||
factory.set_type_override_by_name("uvma_axi_synchronizer_c", "uvma_axi_amo_synchronizer_c");
|
||||
`uvm_info("BASE TEST", $sformatf("AXI AMO SYNCHRONIZER"), UVM_LOW)
|
||||
end
|
||||
|
||||
if(!env_cfg.axi_cfg.preload_mem) begin
|
||||
factory.set_type_override_by_name("uvma_axi_fw_preload_seq_c", "uvme_axi_fw_preload_seq_c");
|
||||
end
|
||||
|
||||
|
||||
endfunction : build_phase
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue