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Add placeholders for PMP CSRs for memory protection.

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Jonathan Richard Robert Kimmitt 2018-03-21 15:19:37 +00:00 • committed by Stefan Mach
parent 9336a95c5f
commit 1ce21e961d
4 changed files with 16 additions and 3 deletions
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2
Makefile
View file

@ -49,7 +49,7 @@ src := $(wildcard src/*.sv) $(wildcard tb/common/*.sv) $(wildcard src/axi2per/*.
tbs := tb/alu_tb.sv tb/core_tb.sv tb/dcache_arbiter_tb.sv tb/store_queue_tb.sv tb/scoreboard_tb.sv tb/fifo_tb.sv
# RISCV-tests path
riscv-test-dir := tmp/riscv-tests/build/isa
riscv-test-dir := $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa
riscv-tests := rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-addw rv64ui-p-and rv64ui-p-auipc \
rv64ui-p-beq rv64ui-p-bge rv64ui-p-bgeu rv64ui-p-andi rv64ui-p-blt rv64ui-p-bltu rv64ui-p-bne \
rv64ui-p-simple rv64ui-p-jal rv64ui-p-jalr rv64ui-p-or rv64ui-p-ori rv64ui-p-sub rv64ui-p-subw \

2
include/ariane_pkg.sv
View file

@ -590,6 +590,8 @@ package ariane_pkg;
CSR_MCAUSE = 12'h342,
CSR_MTVAL = 12'h343,
CSR_MIP = 12'h344,
CSR_PMPCFG0 = 12'h3A0,
CSR_PMPADDR0 = 12'h3B0,
CSR_MVENDORID = 12'hF11,
CSR_MARCHID = 12'hF12,
CSR_MIMPID = 12'hF13,

13
src/csr_regfile.sv
View file

@ -141,6 +141,8 @@ module csr_regfile #(
logic [63:0] medeleg_q, medeleg_d;
logic [63:0] mideleg_q, mideleg_d;
logic [63:0] mip_q, mip_d;
logic [63:0] pmpcfg0_q, pmpcfg0_d;
logic [63:0] pmpaddr0_q, pmpaddr0_d;
logic [63:0] mie_q, mie_d;
logic [63:0] mscratch_q, mscratch_d;
logic [63:0] mepc_q, mepc_d;
@ -216,7 +218,6 @@ module csr_regfile #(
CSR_MISA: csr_rdata = ISA_CODE;
CSR_MEDELEG: csr_rdata = medeleg_q;
CSR_MIDELEG: csr_rdata = mideleg_q;
CSR_MIP: csr_rdata = mip_q;
CSR_MIE: csr_rdata = mie_q;
CSR_MTVEC: csr_rdata = mtvec_q;
CSR_MCOUNTEREN: csr_rdata = 64'b0; // not implemented
@ -224,6 +225,10 @@ module csr_regfile #(
CSR_MEPC: csr_rdata = mepc_q;
CSR_MCAUSE: csr_rdata = mcause_q;
CSR_MTVAL: csr_rdata = mtval_q;
CSR_MIP: csr_rdata = mip_q;
// Placeholders for M-mode protection
CSR_PMPCFG0: csr_rdata = pmpcfg0_q;
CSR_PMPADDR0: csr_rdata = pmpaddr0_q;
CSR_MVENDORID: csr_rdata = 64'b0; // not implemented
CSR_MARCHID: csr_rdata = 64'b0; // PULP, anonymous source (no allocated ID yet)
CSR_MIMPID: csr_rdata = 64'b0; // not implemented
@ -385,7 +390,6 @@ module csr_regfile #(
// mask the register so that unsupported interrupts can never be set
CSR_MIE: mie_d = csr_wdata & 64'hBBB; // we only support supervisor and m-mode interrupts
CSR_MIP: mip_d = mip;
CSR_MTVEC: begin
mtvec_d = {csr_wdata[63:2], 1'b0, csr_wdata[0]};
@ -400,6 +404,11 @@ module csr_regfile #(
CSR_MEPC: mepc_d = {csr_wdata[63:1], 1'b0};
CSR_MCAUSE: mcause_d = csr_wdata;
CSR_MTVAL: mtval_d = csr_wdata;
CSR_MIP: mip_d = mip;
// Placeholders for M-mode protection
CSR_PMPCFG0: pmpcfg0_d = csr_wdata;
CSR_PMPADDR0: pmpaddr0_d = csr_wdata;
CSR_MCYCLE: cycle_d = csr_wdata;
CSR_MINSTRET: instret = csr_wdata;
CSR_DCACHE: dcache_d = csr_wdata[0]; // enable bit

2
src/util/instruction_trace_item.svh
View file

@ -82,6 +82,8 @@ class instruction_trace_item;
CSR_MCAUSE: return "mcause";
CSR_MTVAL: return "mtval";
CSR_MIP: return "mip";
CSR_PMPCFG0: return "pmpcfg0";
CSR_PMPADDR0: return "pmpaddr0";
CSR_MVENDORID: return "mvendorid";
CSR_MARCHID: return "marchid";
CSR_MIMPID: return "mimpid";